conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2022-11-13	Implement CPU halt	Alejandro Soto
2022-11-10	Fix reset glitches	Alejandro Soto
2022-11-10	Fix flush-stall relationship in porch	Alejandro Soto
2022-11-09	Implement reset	Alejandro Soto
2022-11-08	Register decode output in a new porch stage	Alejandro Soto
2022-11-08	Refactor decode signals into unified insn_decode struct	Alejandro Soto
2022-11-07	Fix long combinational path between regs and fetch	Alejandro Soto
2022-11-07	Rework regfile in order to remove negedge trigger	Alejandro Soto
2022-11-07	Implement multiplication control	Alejandro Soto
2022-11-06	Add PSR control signal set	Alejandro Soto
2022-11-06	Implement PSR modes and interrupt masks	Alejandro Soto
2022-11-06	Add multiplier unit	Alejandro Soto
2022-11-02	Use PLL output as CPU clock	Alejandro Soto
2022-11-01	Add the cp15 subsystem	Alejandro Soto
2022-11-01	Implement coprocessor instruction decode	Alejandro Soto
2022-11-01	Add MUL control cycle	Alejandro Soto
2022-11-01	Implement multiplication decode	Alejandro Soto
2022-10-23	Pack general control signals as struct datapath_decode	Alejandro Soto
2022-10-23	Move signal `uses_rn` to struct data_decode	Alejandro Soto
2022-10-23	Move branch control signals to struct branch_decode	Alejandro Soto
2022-10-17	Break false dependency on r0 for MOV/MVN	Alejandro Soto
2022-10-17	Fix data hazards in nzcv and PC increment	Alejandro Soto
2022-10-16	Rename cycles as control	Alejandro Soto
2022-10-15	Fix flags and writeback hazards	Alejandro Soto
2022-10-09	Implement most memory transactions	Alejandro Soto
2022-10-08	Fix writes to PC	Alejandro Soto
2022-10-03	Fix pipeline hazards	Alejandro Soto
2022-10-02	Split decoding of flexible second operand out of data instructions	Alejandro Soto
2022-10-02	Make the fetch stage use the bus arbiter	Alejandro Soto
2022-10-02	Major shifter-ALU redesign	Alejandro Soto
2022-09-27	Switch from operand forwarding to next insn stalls (improves Fmax)	Alejandro Soto
2022-09-27	Implement branching in fetch stage	Alejandro Soto
2022-09-26	Implement ALU shifter	Alejandro Soto
2022-09-25	Define ALU control signal set	Alejandro Soto
2022-09-25	Implement shifter decoding	Alejandro Soto
2022-09-25	Shorten decode_* nets to dec_*	Alejandro Soto
2022-09-25	Implement flag updates	Alejandro Soto
2022-09-25	Refactor CPSR and uarch.sv	Alejandro Soto
2022-09-25	Implement PSR flag handling	Alejandro Soto
2022-09-25	Implement initial cycle control logic	Alejandro Soto
2022-09-24	Implement initial decoder	Alejandro Soto
2022-09-23	Implement core stub	Alejandro Soto