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| author | Alejandro Soto <alejandro@34project.org> | 2022-09-25 23:35:28 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-09-25 23:35:28 -0600 |
| commit | 14d06f0bc047ad79830890807bfe6195ba3de8ff (patch) | |
| tree | 21b252fd9189d91a855342945bb28012ff529d82 /rtl/core/arm810.sv | |
| parent | 43829e0400f0a7aaccbb1ebefb44a38c41749e77 (diff) | |
Define ALU control signal set
Diffstat (limited to 'rtl/core/arm810.sv')
| -rw-r--r-- | rtl/core/arm810.sv | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index 5dc8172..d9939fd 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -49,11 +49,12 @@ module arm810 logic explicit_branch, writeback, update_flags; ptr branch_target; psr_mode reg_mode; - alu_op data_op; + alu_control alu_ctrl; core_cycles cycles ( .branch(explicit_branch), + .alu(alu_ctrl), .* ); @@ -84,7 +85,7 @@ module arm810 core_alu #(.W(32)) alu ( - .op(data_op), + .ctrl(alu_ctrl), .a(rd_value_a), .b(rd_value_b), .c_in(flags.c), |