From 14d06f0bc047ad79830890807bfe6195ba3de8ff Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 25 Sep 2022 23:35:28 -0600 Subject: Define ALU control signal set --- rtl/core/arm810.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'rtl/core/arm810.sv') diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index 5dc8172..d9939fd 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -49,11 +49,12 @@ module arm810 logic explicit_branch, writeback, update_flags; ptr branch_target; psr_mode reg_mode; - alu_op data_op; + alu_control alu_ctrl; core_cycles cycles ( .branch(explicit_branch), + .alu(alu_ctrl), .* ); @@ -84,7 +85,7 @@ module arm810 core_alu #(.W(32)) alu ( - .op(data_op), + .ctrl(alu_ctrl), .a(rd_value_a), .b(rd_value_b), .c_in(flags.c), -- cgit v1.2.3