diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-10-09 19:25:27 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-09 19:25:27 -0600 |
| commit | 7d95ff01bcd8c42efe118fd1bddaabfca0e937eb (patch) | |
| tree | 1d61430989192de9f34fb327772ceff7cac5c71a /rtl/core/arm810.sv | |
| parent | 1f1f61bbab1396278a861e46fd65a50d1914585e (diff) | |
Implement most memory transactions
Diffstat (limited to 'rtl/core/arm810.sv')
| -rw-r--r-- | rtl/core/arm810.sv | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index d3b2c6f..975ce03 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -33,6 +33,7 @@ module arm810 ptr dec_branch_offset; snd_decode dec_snd; data_decode dec_data; + ldst_decode dec_ldst; core_decode decode ( @@ -44,6 +45,7 @@ module arm810 .branch_offset(dec_branch_offset), .snd_ctrl(dec_snd), .data_ctrl(dec_data), + .ldst_ctrl(dec_ldst), .* ); @@ -53,7 +55,7 @@ module arm810 psr_mode reg_mode; alu_op alu_ctrl; shifter_control shifter_ctrl; - word alu_b, wr_value; + word alu_a, alu_b, wr_value; logic[7:0] shifter_shift; core_cycles cycles @@ -61,6 +63,12 @@ module arm810 .branch(explicit_branch), .alu(alu_ctrl), .shifter(shifter_ctrl), + .mem_addr(data_addr), + .mem_start(data_start), + .mem_write(data_write), + .mem_ready(data_ready), + .mem_data_rd(data_data_rd), + .mem_data_wr(data_data_wr), .* ); @@ -93,7 +101,7 @@ module arm810 core_alu #(.W(32)) alu ( .op(alu_ctrl), - .a(rd_value_a), + .a(alu_a), .b(alu_b), .q(q_alu), .nzcv(alu_flags), @@ -114,13 +122,9 @@ module arm810 .c(c_shifter) ); - //TODO ptr data_addr; - logic data_start, data_write, data_ready; - word data_data_rd, data_data_wr; - - logic insn_ready; - word insn_data_rd; + logic data_start, data_write, data_ready, insn_ready; + word data_data_rd, data_data_wr, insn_data_rd; core_mmu mmu ( |