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authorAlejandro Soto <alejandro@34project.org>2022-11-07 17:20:38 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-07 17:25:11 -0600
commitcc7ed6bd05b8143ed4250caf97798c8bbfc6b748 (patch)
tree4fef961873f1a52020ee2cb7c49b59c3fc842c10 /rtl/core/arm810.sv
parent280cb5bb42f56d13ae2043b955a7bf286022b0b7 (diff)
Rework regfile in order to remove negedge trigger
Diffstat (limited to 'rtl/core/arm810.sv')
-rw-r--r--rtl/core/arm810.sv2
1 files changed, 1 insertions, 1 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 3f237aa..5525f95 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -19,7 +19,7 @@ module arm810
core_fetch #(.PREFETCH_ORDER(2)) fetch
(
- .branch(explicit_branch | wr_pc),
+ .branch(explicit_branch || wr_pc),
.flush(0), //TODO
.target(wr_pc ? wr_value[31:2] : branch_target),
.addr(insn_addr),