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2022-12-16Implement IRQ exceptionsAlejandro Soto
2022-12-16Implement prefetch abortsAlejandro Soto
2022-12-16Implement MMU access checksAlejandro Soto
2022-12-16Implement data abortsAlejandro Soto
2022-12-10Expose cp15 signals to core toplevelAlejandro Soto
2022-12-09Implement cp15 controlAlejandro Soto
2022-12-07Implement single-steppingAlejandro Soto
2022-12-06Implement breakpointsAlejandro Soto
2022-11-16Implement psr read/write logicAlejandro Soto
2022-11-16Simplify flags datapathAlejandro Soto
2022-11-16Finish decode of psr operationsAlejandro Soto
2022-11-15Implemente byte-enable signal in storesAlejandro Soto
2022-11-15Implement sub-word memory accessesAlejandro Soto
2022-11-15Mpve combinational logic out of arm810.svAlejandro Soto
2022-11-13Implement CPU haltAlejandro Soto
2022-11-10Fix reset glitchesAlejandro Soto
2022-11-10Fix flush-stall relationship in porchAlejandro Soto
2022-11-09Implement resetAlejandro Soto
2022-11-08Register decode output in a new porch stageAlejandro Soto
2022-11-08Refactor decode signals into unified insn_decode structAlejandro Soto
2022-11-07Fix long combinational path between regs and fetchAlejandro Soto
2022-11-07Rework regfile in order to remove negedge triggerAlejandro Soto
2022-11-07Implement multiplication controlAlejandro Soto
2022-11-06Add PSR control signal setAlejandro Soto
2022-11-06Implement PSR modes and interrupt masksAlejandro Soto
2022-11-06Add multiplier unitAlejandro Soto
2022-11-02Use PLL output as CPU clockAlejandro Soto
2022-11-01Add the cp15 subsystemAlejandro Soto
2022-11-01Implement coprocessor instruction decodeAlejandro Soto
2022-11-01Add MUL control cycleAlejandro Soto
2022-11-01Implement multiplication decodeAlejandro Soto
2022-10-23Pack general control signals as struct datapath_decodeAlejandro Soto
2022-10-23Move signal `uses_rn` to struct data_decodeAlejandro Soto
2022-10-23Move branch control signals to struct branch_decodeAlejandro Soto
2022-10-17Break false dependency on r0 for MOV/MVNAlejandro Soto
2022-10-17Fix data hazards in nzcv and PC incrementAlejandro Soto
2022-10-16Rename cycles as controlAlejandro Soto
2022-10-15Fix flags and writeback hazardsAlejandro Soto
2022-10-09Implement most memory transactionsAlejandro Soto
2022-10-08Fix writes to PCAlejandro Soto
2022-10-03Fix pipeline hazardsAlejandro Soto
2022-10-02Split decoding of flexible second operand out of data instructionsAlejandro Soto
2022-10-02Make the fetch stage use the bus arbiterAlejandro Soto
2022-10-02Major shifter-ALU redesignAlejandro Soto
The shifter unit now works in parallel with the ALU and is no longer part of it. Instructions that use the shifter as input to the ALU will now take an additional cycle, unless the control unit can detect a "trivial shift" situation where the shifter's output will be the same as its input. This change improves Fmax substantially.
2022-09-27Switch from operand forwarding to next insn stalls (improves Fmax)Alejandro Soto
2022-09-27Implement branching in fetch stageAlejandro Soto
2022-09-26Implement ALU shifterAlejandro Soto
2022-09-25Define ALU control signal setAlejandro Soto
2022-09-25Implement shifter decodingAlejandro Soto
2022-09-25Shorten decode_* nets to dec_*Alejandro Soto
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