conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2023-10-04	sram comments	JulianCamacho
2023-10-04	fix typo	Fabian Montero
2023-10-04	explica composición de cache en archivo SRAM.	Fabian Montero
2023-10-04	improve comments	Fabian Montero
2023-10-04	sram comment	JulianCamacho
2023-10-04	Merge remote-tracking branch 'origin/comentarios' into arqui2	Alejandro Soto
2023-10-04	explica mejor las transiciones de routing	Fabian Montero
2023-10-04	explica estados de routing	Fabian Montero
2023-10-04	rtl/cache: increase to 64KiB per core	Alejandro Soto
2023-10-04	rtl/cache: implement debug interface	Alejandro Soto
2023-10-04	routing and beginning cache control comments	JulianCamacho
2023-10-03	sram, offset and routing comments	JulianCamacho
2023-10-03	rtl/cache: implement ll/sc line monitor	Alejandro Soto
2023-10-03	rtl/core/control: reject strex after exceptions	Alejandro Soto
2023-10-03	comentarios	JulianCamacho
2023-10-02	rtl/cache: fix coherence bug during snoops (in_hold latched too early)	Alejandro Soto
2023-10-02	rtl/core/control: implement exclusive ldst	Alejandro Soto
2023-10-02	rtl/core: implement ldrex/strex decode	Alejandro Soto
2023-10-02	rtl: implement exclusive monitor datapath	Alejandro Soto
2023-10-01	rtl/cache: fix controller deadlock on cache-cache reply	Alejandro Soto
2023-10-01	rtl/smp: fix step-on-reset bug	Alejandro Soto
2023-10-01	tb: implement quad-core SMP	Alejandro Soto
2023-09-30	platform: implement SMP controller	Alejandro Soto
2023-09-29	platform: add CPUs and caches to qsys	Alejandro Soto
2023-09-26	rtl/mp: fix design	Alejandro Soto
2023-09-26	rtl/mp: add initial version of mp	JulianCamacho
2023-09-25	rtl/core, tb: replace bus_master with a new top-level module	Alejandro Soto
2023-09-25	rtl/cache: fix writeback corruption	Alejandro Soto
2023-09-25	rtl/cache: implement wait-for-reply	Alejandro Soto
2023-09-24	rtl/cache: implement	Alejandro Soto
2022-12-21	Fix clock/reset timing in single-step, dsp_mul	Alejandro Soto
2022-12-19	Fix spurious high bus_write in page walker	Alejandro Soto
2022-12-18	Implement privileged ldm/stm of user registers	Alejandro Soto
2022-12-18	Implement mode-translated memory accesses	Alejandro Soto
2022-12-18	Fix datapath of shifter carry-out during adc/sbc/rsc	Alejandro Soto
2022-12-16	Fix privilege escalation while in user mode	Alejandro Soto
2022-12-16	Implement mode privilege checks in MMU	Alejandro Soto
2022-12-16	Add interrupt controller to Platform Designer	Alejandro Soto
2022-12-16	Implement swi (system call)	Alejandro Soto
2022-12-16	Implement branch history (simulation only)	Alejandro Soto
2022-12-16	Fix register corruption when interrupting a load-store	Alejandro Soto
2022-12-16	Fix implementation of MMU access faults	Alejandro Soto
2022-12-16	Implement interrupt emulation	Alejandro Soto
2022-12-16	Implement IRQ exceptions	Alejandro Soto
2022-12-16	Implement interrupt controller	Alejandro Soto
2022-12-16	Add cp15 cyclecnt clock source	Alejandro Soto
2022-12-16	Fix sysctrl register dump	Alejandro Soto
2022-12-16	Show main cp15 registers in register dumps	Alejandro Soto
2022-12-16	Implement prefetch aborts	Alejandro Soto
2022-12-16	Implement register writes from gdb	Alejandro Soto