Implement mode-translated memory accesses

5 files changed, 14 insertions, 3 deletions

diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 8ebabc1..1c9d449 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -77,6 +77,7 @@ module arm810
 		.branch(explicit_branch),
 		.shifter(shifter_ctrl),
 		.mem_addr(data_addr),
+		.mem_user(data_user),
 		.mem_start(data_start),
 		.mem_write(data_write),
 		.mem_ready(data_ready),
@@ -174,9 +175,11 @@ module arm810
 
 	ptr data_addr;
 	word data_data_rd, data_data_wr, insn_data_rd;
-	logic data_start, data_write, data_ready, insn_ready, data_fault, insn_fault;
 	logic[3:0] data_data_be;
 
+	logic data_start, data_write, data_ready, insn_ready,
+	      data_fault, insn_fault, data_user;
+
 	core_mmu mmu
 	(
 		.*
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index a421572..cab47ce 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -61,6 +61,7 @@ module core_control
 	output logic[3:0]      mem_data_be,
 	output logic           mem_start,
 	                       mem_write,
+	                       mem_user,
 	output word            mul_a,
 	                       mul_b,
 	                       mul_c_hi,
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv
index c8f0dcb..bb057bb 100644
--- a/rtl/core/control/ldst/ldst.sv
+++ b/rtl/core/control/ldst/ldst.sv
@@ -23,6 +23,7 @@ module core_control_ldst
 	                   mem_offset,
 	output logic       mem_start,
 	                   mem_write,
+	                   mem_user,
 	                   pop_valid,
 	                   ldst,
 	                   ldst_next,
@@ -73,6 +74,7 @@ module core_control_ldst
 
 			base <= {$bits(base){1'b0}};
 			mem_regs <= {$bits(mem_regs){1'b0}};
+			mem_user <= 0;
 			mem_write <= 0;
 			mem_start <= 0;
 			mem_offset <= 0;
@@ -81,9 +83,10 @@ module core_control_ldst
 				mem_start <= 0;
 
 			if(next_cycle.issue) begin
-				// TODO: dec.ldst.unprivileged
-				if(issue)
+				if(issue) begin
 					ldst <= dec.ctrl.ldst;
+					mem_user <= dec.ldst.unprivileged;
+				end
 
 				pre <= dec.ldst.pre_indexed;
 				size <= dec.ldst.size;
diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv
index f8e808b..b6c3668 100644
--- a/rtl/core/mmu/mmu.sv
+++ b/rtl/core/mmu/mmu.sv
@@ -19,6 +19,7 @@ module core_mmu
 	input  logic          insn_start,
 	                      data_start,
 	                      data_write,
+	                      data_user,
 	input  logic[3:0]     data_data_be,
 
 	output word           bus_data_wr,
@@ -96,6 +97,7 @@ module core_mmu
 		.bus_data_be(dphys_data_be),
 		.bus_data_rd(dphys_data_rd),
 
+		.privileged(privileged && !data_user),
 		.*
 	);
 
diff --git a/rtl/core/porch/porch.sv b/rtl/core/porch/porch.sv
index 99ba9ed..060ab91 100644
--- a/rtl/core/porch/porch.sv
+++ b/rtl/core/porch/porch.sv
@@ -24,6 +24,8 @@ module core_porch
 	logic execute, conditional, undefined, nop;
 	insn_decode hold_dec;
 
+	//FIXME: User mode puede hacer msr o mcr y saltare cualquier límite de seguridad
+
 	always_comb begin
 		dec = hold_dec;
 		dec.ctrl.nop = nop;