diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-09-25 16:47:45 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-09-25 16:56:06 -0600 |
| commit | cd02f821525b8710dd37e2bc39a8a7dbc36ac4b0 (patch) | |
| tree | ae6d853ae4531027f4f5bb7e9a4a4b3dd9facda4 /rtl | |
| parent | d18a37a740db37707e5266e5ca6a8fd956737197 (diff) | |
rtl/cache: fix writeback corruption
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/cache/control.sv | 8 | ||||
| -rw-r--r-- | rtl/cache/routing.sv | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/rtl/cache/control.sv b/rtl/cache/control.sv index a930e87..73eb644 100644 --- a/rtl/cache/control.sv +++ b/rtl/cache/control.sv @@ -84,13 +84,13 @@ module cache_control assign may_send = may_send_if_token_held && in_token_valid; assign may_send_if_token_held - = (!in_token.e2.valid || in_token.e2.index != core_index || in_token.e2.tag != core_tag) - && (!in_token.e1.valid || in_token.e1.index != core_index || in_token.e1.tag != core_tag) - && (!in_token.e0.valid || in_token.e0.index != core_index || in_token.e0.tag != core_tag); + = (!in_token.e2.valid || in_token.e2.index != core_index || in_token.e2.tag != core_tag) + && (!in_token.e1.valid || in_token.e1.index != core_index || in_token.e1.tag != core_tag) + && (!in_token.e0.valid || in_token.e0.index != core_index || in_token.e0.tag != core_tag); assign out_data = out_stall ? stall_data : out_data_next; assign out_data_next = send ? send_data : fwd_data; - assign out_data_valid = out_stall || send || (in_hold_valid && !last_hop); + assign out_data_valid = out_stall || send || (in_hold_valid && !last_hop && in_data_ready); assign send_data.tag = core_tag; assign send_data.ttl = `TTL_MAX; diff --git a/rtl/cache/routing.sv b/rtl/cache/routing.sv index 45e0296..c72d9b5 100644 --- a/rtl/cache/routing.sv +++ b/rtl/cache/routing.sv @@ -100,7 +100,7 @@ module cache_routing if (transition) begin mem_address <= cache_mem ? cache_mem_address : core_address_line; mem_writedata <= cache_mem ? cache_mem_writedata : core_writedata_line; - mem_byteenable <= cache_mem ? 16'hff : core_byteenable_line; + mem_byteenable <= cache_mem ? 16'hffff : core_byteenable_line; end endmodule |