| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-12-16 | Add cp15 cyclecnt clock source | Alejandro Soto |
| 2022-12-16 | Fix sysctrl register dump | Alejandro Soto |
| 2022-12-16 | Show main cp15 registers in register dumps | Alejandro Soto |
| 2022-12-16 | Implement MMU access checks | Alejandro Soto |
| 2022-12-16 | Implement data aborts | Alejandro Soto |
| 2022-12-10 | Expose cp15 signals to core toplevel | Alejandro Soto |
| 2022-12-10 | Implement rest of cp15 registers | Alejandro Soto |
| 2022-12-09 | Implement CP15 ID register | Alejandro Soto |
| 2022-11-09 | Implement reset | Alejandro Soto |
| 2022-11-01 | Add CPUID register | Alejandro Soto |
| 2022-11-01 | Add cp15 primary register map | Alejandro Soto |
| 2022-11-01 | Add the cp15 subsystem | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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