| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-10-03 | rtl/core/control: reject strex after exceptions | Alejandro Soto | |
| 2022-12-16 | Implement data aborts | Alejandro Soto | |
| 2022-12-09 | Implement cp15 control | Alejandro Soto | |
| 2022-11-16 | Implement privilege escalation | Alejandro Soto | |
| 2022-11-16 | Implement psr read/write logic | Alejandro Soto | |
| 2022-11-13 | Fix big Quartus state transition bug | Alejandro Soto | |
| 2022-11-13 | Convert core state machines to Quartus-inferring RTL | Alejandro Soto | |
| 2022-11-13 | Implement CPU halt | Alejandro Soto | |
| 2022-11-09 | Implement reset | Alejandro Soto | |
| 2022-11-07 | Quartus has not support for unique0 | Alejandro Soto | |
| 2022-11-07 | Implement multiplication control | Alejandro Soto | |
| 2022-11-01 | Add MUL control cycle | Alejandro Soto | |
| 2022-10-24 | Split cycle logic out of control.sv | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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