diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-12 21:47:54 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-13 05:54:44 -0600 |
| commit | 6cb000adf57d7af2ec4aac8fd93d12f09cc63556 (patch) | |
| tree | 39610a5bd40d8fbb5b0ffd54252113f859dc3c71 /rtl/core/control/cycles.sv | |
| parent | 6281f45ac01e113f2b59fe6f49baad0cc8ab16fc (diff) | |
Implement CPU halt
Diffstat (limited to 'rtl/core/control/cycles.sv')
| -rw-r--r-- | rtl/core/control/cycles.sv | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv index 0a70d5e..0c5d94c 100644 --- a/rtl/core/control/cycles.sv +++ b/rtl/core/control/cycles.sv @@ -4,6 +4,7 @@ module core_control_cycles ( input logic clk, rst_n, + halt, mul, ldst, bubble, @@ -28,6 +29,8 @@ module core_control_cycles ISSUE: if(exception) next_cycle = EXCEPTION; + else if(halt) + next_cycle = ISSUE; else if(mul) next_cycle = mul_add ? MUL_ACC_LD : MUL; else if(data_snd_shift_by_reg) |