From 6cb000adf57d7af2ec4aac8fd93d12f09cc63556 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 12 Nov 2022 21:47:54 -0600 Subject: Implement CPU halt --- rtl/core/control/cycles.sv | 3 +++ 1 file changed, 3 insertions(+) (limited to 'rtl/core/control/cycles.sv') diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv index 0a70d5e..0c5d94c 100644 --- a/rtl/core/control/cycles.sv +++ b/rtl/core/control/cycles.sv @@ -4,6 +4,7 @@ module core_control_cycles ( input logic clk, rst_n, + halt, mul, ldst, bubble, @@ -28,6 +29,8 @@ module core_control_cycles ISSUE: if(exception) next_cycle = EXCEPTION; + else if(halt) + next_cycle = ISSUE; else if(mul) next_cycle = mul_add ? MUL_ACC_LD : MUL; else if(data_snd_shift_by_reg) -- cgit v1.2.3