diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-12-11 14:48:08 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-16 16:27:20 -0600 |
| commit | ff71bcd0c5425c168f111b8f4a92d0a90a6c9c31 (patch) | |
| tree | 41190239b9220db09d8849afb6d6f6dbbc03f59b /rtl/core/control/cycles.sv | |
| parent | 6fee344b754464b1fd17f7c0429e6597e51dc74d (diff) | |
Implement data aborts
Diffstat (limited to 'rtl/core/control/cycles.sv')
| -rw-r--r-- | rtl/core/control/cycles.sv | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv index 88e0235..5779990 100644 --- a/rtl/core/control/cycles.sv +++ b/rtl/core/control/cycles.sv @@ -12,6 +12,7 @@ module core_control_cycles coproc, exception, mem_ready, + mem_fault, mul_add, mul_long, mul_ready, @@ -100,12 +101,16 @@ module core_control_cycles ESCALATE: next_state = EXCEPTION; - TRANSFER: + TRANSFER: begin if(!mem_ready || pop_valid) next_state = TRANSFER; else if(ldst_writeback) next_state = BASE_WRITEBACK; + if(mem_ready && mem_fault) + next_state = ESCALATE; + end + MUL: if(!mul_ready) next_state = MUL; |