From ff71bcd0c5425c168f111b8f4a92d0a90a6c9c31 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 11 Dec 2022 14:48:08 -0600
Subject: Implement data aborts

---
 rtl/core/control/cycles.sv | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'rtl/core/control/cycles.sv')

diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv
index 88e0235..5779990 100644
--- a/rtl/core/control/cycles.sv
+++ b/rtl/core/control/cycles.sv
@@ -12,6 +12,7 @@ module core_control_cycles
 	                  coproc,
 	                  exception,
 	                  mem_ready,
+	                  mem_fault,
 	                  mul_add,
 	                  mul_long,
 	                  mul_ready,
@@ -100,12 +101,16 @@ module core_control_cycles
 			ESCALATE:
 				next_state = EXCEPTION;
 
-			TRANSFER:
+			TRANSFER: begin
 				if(!mem_ready || pop_valid)
 					next_state = TRANSFER;
 				else if(ldst_writeback)
 					next_state = BASE_WRITEBACK;
 
+				if(mem_ready && mem_fault)
+					next_state = ESCALATE;
+			end
+
 			MUL:
 				if(!mul_ready)
 					next_state = MUL;
-- 
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