Implement reset

1 files changed, 3 insertions, 5 deletions

diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv
index f6bc517..0a70d5e 100644
--- a/rtl/core/control/cycles.sv
+++ b/rtl/core/control/cycles.sv
@@ -3,6 +3,7 @@
 module core_control_cycles
 (
 	input  logic      clk,
+	                  rst_n,
 	                  mul,
 	                  ldst,
 	                  bubble,
@@ -61,10 +62,7 @@ module core_control_cycles
 		end
 	end
 
-	always_ff @(posedge clk)
-		cycle <= next_cycle;
-
-	initial
-		cycle = ISSUE;
+	always_ff @(posedge clk or negedge rst_n)
+		cycle <= !rst_n ? ISSUE : next_cycle;
 
 endmodule