From 5d798386c3b1c1dc45a2fbc382c9367ccc27c524 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 9 Nov 2022 09:25:48 -0600 Subject: Implement reset --- rtl/core/control/cycles.sv | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'rtl/core/control/cycles.sv') diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv index f6bc517..0a70d5e 100644 --- a/rtl/core/control/cycles.sv +++ b/rtl/core/control/cycles.sv @@ -3,6 +3,7 @@ module core_control_cycles ( input logic clk, + rst_n, mul, ldst, bubble, @@ -61,10 +62,7 @@ module core_control_cycles end end - always_ff @(posedge clk) - cycle <= next_cycle; - - initial - cycle = ISSUE; + always_ff @(posedge clk or negedge rst_n) + cycle <= !rst_n ? ISSUE : next_cycle; endmodule -- cgit v1.2.3