Implement reset

12 files changed, 145 insertions, 149 deletions

diff --git a/rtl/core/control/branch.sv b/rtl/core/control/branch.sv
index 59a4f54..96e6e65 100644
--- a/rtl/core/control/branch.sv
+++ b/rtl/core/control/branch.sv
@@ -3,6 +3,7 @@
 module core_control_branch
 (
 	input  logic       clk,
+	                   rst_n,
 
 	input  insn_decode dec,
 
@@ -14,17 +15,16 @@ module core_control_branch
 	output ptr         branch_target
 );
 
-	always_ff @(posedge clk) begin
-		branch <= 0;
-		if(next_cycle == ISSUE && issue) begin
-			branch <= dec.ctrl.branch;
-			branch_target <= next_pc_visible + dec.branch.offset;
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			branch <= 1;
+			branch_target <= {$bits(branch_target){1'b0}};
+		end else begin
+			branch <= 0;
+			if(next_cycle == ISSUE && issue) begin
+				branch <= dec.ctrl.branch;
+				branch_target <= next_pc_visible + dec.branch.offset;
+			end
 		end
-	end
-
-	initial begin
-		branch = 1;
-		branch_target = {$bits(branch_target){1'b0}};
-	end
 
 endmodule
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 077ba1c..45e8e10 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -3,6 +3,8 @@
 module core_control
 (
 	input  logic           clk,
+	                       rst_n,
+
 	input  insn_decode     dec,
 	input  ptr             insn_pc,
 	input  psr_flags       flags,
diff --git a/rtl/core/control/coproc.sv b/rtl/core/control/coproc.sv
index b0c8bea..a457b0f 100644
--- a/rtl/core/control/coproc.sv
+++ b/rtl/core/control/coproc.sv
@@ -3,6 +3,7 @@
 module core_control_coproc
 (
 	input  logic       clk,
+	                   rst_n,
 
 	input  insn_decode dec,
 
@@ -12,11 +13,10 @@ module core_control_coproc
 	output logic       coproc
 );
 
-	always_ff @(posedge clk)
-		if(next_cycle == ISSUE && issue)
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n)
+			coproc <= 0;
+		else if(next_cycle == ISSUE && issue)
 			coproc <= dec.ctrl.coproc;
 
-	initial
-		coproc = 0;
-
 endmodule
diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv
index f6bc517..0a70d5e 100644
--- a/rtl/core/control/cycles.sv
+++ b/rtl/core/control/cycles.sv
@@ -3,6 +3,7 @@
 module core_control_cycles
 (
 	input  logic      clk,
+	                  rst_n,
 	                  mul,
 	                  ldst,
 	                  bubble,
@@ -61,10 +62,7 @@ module core_control_cycles
 		end
 	end
 
-	always_ff @(posedge clk)
-		cycle <= next_cycle;
-
-	initial
-		cycle = ISSUE;
+	always_ff @(posedge clk or negedge rst_n)
+		cycle <= !rst_n ? ISSUE : next_cycle;
 
 endmodule
diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv
index 0d87b02..fc936dc 100644
--- a/rtl/core/control/data.sv
+++ b/rtl/core/control/data.sv
@@ -3,6 +3,7 @@
 module core_control_data
 (
 	input  logic           clk,
+	                       rst_n,
 
 	input  insn_decode     dec,
 	input  word            rd_value_a,
@@ -62,8 +63,16 @@ module core_control_data
 		endcase
 	end
 
-	always_ff @(posedge clk)
-		unique case(next_cycle)
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			alu <= {$bits(alu){1'b0}};
+			c_in <= 0;
+			shifter <= {$bits(shifter){1'b0}};
+			data_imm <= {$bits(data_imm){1'b0}};
+			data_shift_imm <= {$bits(data_shift_imm){1'b0}};
+			data_snd_is_imm <= 0;
+			data_snd_shift_by_reg <= 0;
+		end else unique case(next_cycle)
 			ISSUE: begin
 				alu <= dec.data.op;
 				c_in <= flags.c;
@@ -100,14 +109,4 @@ module core_control_data
 			end
 		endcase
 
-	initial begin
-		alu = {$bits(alu){1'b0}};
-		c_in = 0;
-		shifter = {$bits(shifter){1'b0}};
-		data_imm = {$bits(data_imm){1'b0}};
-		data_shift_imm = {$bits(data_shift_imm){1'b0}};
-		data_snd_is_imm = 0;
-		data_snd_shift_by_reg = 0;
-	end
-
 endmodule
diff --git a/rtl/core/control/exception.sv b/rtl/core/control/exception.sv
index 9a64cd5..c4f3772 100644
--- a/rtl/core/control/exception.sv
+++ b/rtl/core/control/exception.sv
@@ -3,6 +3,7 @@
 module core_control_exception
 (
 	input  logic clk,
+	             rst_n,
 
 	input  logic undefined,
 
diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv
index e3644c4..e3eb338 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/control/issue.sv
@@ -3,6 +3,7 @@
 module core_control_issue
 (
 	input  logic       clk,
+	                   rst_n,
 
 	input  insn_decode dec,
 	input  ptr         insn_pc,
@@ -24,8 +25,12 @@ module core_control_issue
 	assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble;
 	assign next_pc_visible = insn_pc + 2;
 
-	always_ff @(posedge clk)
-		if(next_cycle == ISSUE) begin
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			pc <= 0;
+			undefined <= 0;
+			pc_visible <= 2;
+		end else if(next_cycle == ISSUE) begin
 			undefined <= dec.ctrl.undefined;
 
 `ifdef VERILATOR
@@ -37,10 +42,4 @@ module core_control_issue
 			pc_visible <= next_pc_visible;
 		end
 
-	initial begin
-		pc = 0;
-		pc_visible = 2;
-		undefined = 0;
-	end
-
 endmodule
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv
index 2a295c8..baf0054 100644
--- a/rtl/core/control/ldst/ldst.sv
+++ b/rtl/core/control/ldst/ldst.sv
@@ -3,6 +3,7 @@
 module core_control_ldst
 (
 	input  logic       clk,
+	                   rst_n,
 
 	input  insn_decode dec,
 	input  logic       issue,
@@ -43,8 +44,19 @@ module core_control_ldst
 		.pop_lower(popped_lower)
 	);
 
-	always_ff @(posedge clk)
-		unique case(next_cycle)
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			ldst <= 0;
+			ldst_pre <= 0;
+			ldst_writeback <= 0;
+			ldst_increment <= 0;
+
+			mem_addr <= {$bits(mem_addr){1'b0}};
+			mem_write <= 0;
+			mem_start <= 0;
+			mem_regs <= {$bits(mem_regs){1'b0}};
+			mem_offset <= 0;
+		end else unique case(next_cycle)
 			ISSUE: begin
 				// TODO: dec.ldst.unprivileged/user_regs
 				// TODO: byte/halfword sizes
@@ -74,17 +86,4 @@ module core_control_ldst
 			end
 		endcase
 
-	initial begin
-		ldst = 0;
-		ldst_pre = 0;
-		ldst_writeback = 0;
-		ldst_increment = 0;
-
-		mem_addr = {$bits(mem_addr){1'b0}};
-		mem_write = 0;
-		mem_start = 0;
-		mem_regs = {$bits(mem_regs){1'b0}};
-		mem_offset = 0;
-	end
-
 endmodule
diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv
index 8f7cd91..9e66053 100644
--- a/rtl/core/control/mul.sv
+++ b/rtl/core/control/mul.sv
@@ -3,6 +3,7 @@
 module core_control_mul
 (
 	input  logic       clk,
+	                   rst_n,
 
 	input  insn_decode dec,
 	input  logic       mul_ready,
@@ -31,42 +32,41 @@ module core_control_mul
 	assign {mul_c_hi, mul_c_lo} = {rd_value_a, rd_value_b};
 	assign {mul_a, mul_b} = mul_add ? {hold_a, hold_b} : {rd_value_a, rd_value_b};
 
-	always_ff @(posedge clk) begin
-		mul_start <= 0;
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			mul <= 0;
+			mul_add <= 0;
+			mul_long <= 0;
+			mul_start <= 0;
+			mul_signed <= 0;
+			mul_r_add_hi <= {$bits(mul_r_add_hi){1'b0}};
+			mul_r_add_lo <= {$bits(mul_r_add_lo){1'b0}};
 
-		unique case(next_cycle)
-			ISSUE: begin
-				mul <= issue && dec.ctrl.mul;
-				mul_add <= dec.mul.add;
-				mul_long <= dec.mul.long_mul;
-				mul_signed <= dec.mul.signed_mul;
-				mul_r_add_hi <= dec.mul.r_add_hi;
-				mul_r_add_lo <= dec.mul.r_add_lo;
-			end
+			hold_a <= 0;
+			hold_b <= 0;
+		end else begin
+			mul_start <= 0;
 
-			MUL:
-				mul_start <= cycle != MUL;
+			unique case(next_cycle)
+				ISSUE: begin
+					mul <= issue && dec.ctrl.mul;
+					mul_add <= dec.mul.add;
+					mul_long <= dec.mul.long_mul;
+					mul_signed <= dec.mul.signed_mul;
+					mul_r_add_hi <= dec.mul.r_add_hi;
+					mul_r_add_lo <= dec.mul.r_add_lo;
+				end
 
-			MUL_ACC_LD: begin
-				hold_a <= rd_value_a;
-				hold_b <= rd_value_b;
-			end
-		endcase
-	end
+				MUL:
+					mul_start <= cycle != MUL;
 
-	//TODO: mul update_flags
-
-	initial begin
-		mul = 0;
-		mul_add = 0;
-		mul_long = 0;
-		mul_start = 0;
-		mul_signed = 0;
-		mul_r_add_hi = {$bits(mul_r_add_hi){1'b0}};
-		mul_r_add_lo = {$bits(mul_r_add_lo){1'b0}};
+				MUL_ACC_LD: begin
+					hold_a <= rd_value_a;
+					hold_b <= rd_value_b;
+				end
+			endcase
+		end
 
-		hold_a = 0;
-		hold_b = 0;
-	end
+	//TODO: mul update_flags
 
 endmodule
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv
index 09fb144..80a437f 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/control/select.sv
@@ -3,6 +3,7 @@
 module core_control_select
 (
 	input  logic       clk,
+	                   rst_n,
 
 	input  insn_decode dec,
 
@@ -46,18 +47,17 @@ module core_control_select
 		endcase
 	end
 
-	always_ff @(posedge clk) begin
-		last_ra <= ra;
-		last_rb <= rb;
-
-		if(next_cycle == ISSUE)
-			r_shift <= dec.snd.r_shift;
-	end
-
-	initial begin
-		last_ra = {$bits(ra){1'b0}};
-		last_rb = {$bits(rb){1'b0}};
-		r_shift = {$bits(r_shift){1'b0}};
-	end
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			last_ra <= {$bits(ra){1'b0}};
+			last_rb <= {$bits(rb){1'b0}};
+			r_shift <= {$bits(r_shift){1'b0}};
+		end else begin
+			last_ra <= ra;
+			last_rb <= rb;
+
+			if(next_cycle == ISSUE)
+				r_shift <= dec.snd.r_shift;
+		end
 
 endmodule
diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv
index 223fecb..60dfbbe 100644
--- a/rtl/core/control/stall.sv
+++ b/rtl/core/control/stall.sv
@@ -3,6 +3,7 @@
 module core_control_stall
 (
 	input  logic       clk,
+	                   rst_n,
 
 	input  insn_decode dec,
 
@@ -33,10 +34,7 @@ module core_control_stall
 	assign flags_dependency = dec.psr.update_flags || dec.ctrl.conditional;
 	assign updating_flags = final_update_flags || update_flags;
 
-	always_ff @(posedge clk)
-		bubble <= next_cycle == ISSUE && next_bubble;
-
-	initial
-		bubble = 0;
+	always_ff @(posedge clk or negedge rst_n)
+		bubble <= !rst_n ? 0 : next_cycle == ISSUE && next_bubble;
 
 endmodule
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index 73a8a4c..1fb3ced 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -3,6 +3,7 @@
 module core_control_writeback
 (
 	input  logic       clk,
+	                   rst_n,
 
 	input  insn_decode dec,
 	input  psr_flags   alu_flags,
@@ -100,60 +101,59 @@ module core_control_writeback
 		endcase
 	end
 
-	always_ff @(posedge clk) begin
-		last_rd <= rd;
-		wb_alu_flags <= alu_flags;
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			last_rd <= 0;
+			final_rd <= 0;
+			final_writeback <= 0;
 
-		unique case(next_cycle)
-			ISSUE:
-				final_rd <= dec.data.rd;
+			update_flags <= 0;
+			final_update_flags <= 0;
 
-			TRANSFER:
-				if((cycle != TRANSFER || mem_ready) && pop_valid)
-					final_rd <= popped;
+			wb_alu_flags <= {$bits(wb_alu_flags){1'b0}};
+		end else begin
+			last_rd <= rd;
+			wb_alu_flags <= alu_flags;
 
-			BASE_WRITEBACK:
-				final_rd <= ra;
+			unique case(next_cycle)
+				ISSUE:
+					final_rd <= dec.data.rd;
 
-			EXCEPTION:
-				final_rd <= `R14;
-		endcase
+				TRANSFER:
+					if((cycle != TRANSFER || mem_ready) && pop_valid)
+						final_rd <= popped;
 
-		unique case(next_cycle)
-			ISSUE:
-				final_writeback <= issue && dec.ctrl.writeback;
+				BASE_WRITEBACK:
+					final_rd <= ra;
 
-			EXCEPTION:
-				final_writeback <= 1;
-		endcase
+				EXCEPTION:
+					final_rd <= `R14;
+			endcase
 
-		update_flags <= 0;
-		unique case(next_cycle)
-			ISSUE:
-				update_flags <= final_update_flags;
+			unique case(next_cycle)
+				ISSUE:
+					final_writeback <= issue && dec.ctrl.writeback;
 
-			EXCEPTION:
-				final_update_flags <= 0;
-		endcase
-
-		unique case(next_cycle)
-			ISSUE:
-				final_update_flags <= issue && dec.psr.update_flags;
+				EXCEPTION:
+					final_writeback <= 1;
+			endcase
 
-			EXCEPTION:
-				final_update_flags <= 0;
-		endcase
-	end
+			update_flags <= 0;
+			unique case(next_cycle)
+				ISSUE:
+					update_flags <= final_update_flags;
 
-	initial begin
-		last_rd = 0;
-		final_rd = 0;
-		final_writeback = 0;
+				EXCEPTION:
+					final_update_flags <= 0;
+			endcase
 
-		update_flags = 0;
-		final_update_flags = 0;
+			unique case(next_cycle)
+				ISSUE:
+					final_update_flags <= issue && dec.psr.update_flags;
 
-		wb_alu_flags = {$bits(wb_alu_flags){1'b0}};
-	end
+				EXCEPTION:
+					final_update_flags <= 0;
+			endcase
+		end
 
 endmodule