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AgeCommit message (Collapse)Author
2023-10-02rtl: implement exclusive monitor datapathAlejandro Soto
2022-12-18Implement privileged ldm/stm of user registersAlejandro Soto
2022-12-18Implement mode-translated memory accessesAlejandro Soto
2022-12-18Fix datapath of shifter carry-out during adc/sbc/rscAlejandro Soto
2022-12-16Fix privilege escalation while in user modeAlejandro Soto
2022-12-16Implement IRQ exceptionsAlejandro Soto
2022-12-16Implement prefetch abortsAlejandro Soto
2022-12-16Implement data abortsAlejandro Soto
2022-12-10Expose cp15 signals to core toplevelAlejandro Soto
2022-12-09Implement cp15 controlAlejandro Soto
2022-12-07Implement single-steppingAlejandro Soto
2022-12-06Implement breakpointsAlejandro Soto
2022-11-16Implement psr read/write logicAlejandro Soto
2022-11-16Simplify flags datapathAlejandro Soto
2022-11-15Implemente byte-enable signal in storesAlejandro Soto
2022-11-15Implement sub-word memory accessesAlejandro Soto
2022-11-15Rewrite duplicate ldst logic as signal ldst_nextAlejandro Soto
2022-11-13Implement CPU haltAlejandro Soto
2022-11-09Implement resetAlejandro Soto
2022-11-08Register decode output in a new porch stageAlejandro Soto
2022-11-08Refactor decode signals into unified insn_decode structAlejandro Soto
2022-11-07Implement multiplication controlAlejandro Soto
2022-11-06Add PSR control signal setAlejandro Soto
2022-11-06Clean-up control.svAlejandro Soto
2022-11-06Move CP15 logic out of control.svAlejandro Soto
2022-11-06Move multiplication logic out of control.svAlejandro Soto
2022-11-06Move load-store logic out of control.svAlejandro Soto
2022-11-06Split regfile read select logic out of control.svAlejandro Soto
2022-11-06Move exception logic out of control.svAlejandro Soto
2022-11-06Move flag update logic to writeback.svAlejandro Soto
2022-11-06Split ALU/shifter control logic out of control.svAlejandro Soto
2022-11-06Split branch logic out of control.svAlejandro Soto
2022-11-06Multiplex writeback control signalsAlejandro Soto
2022-11-06Split issue logic out of control.svAlejandro Soto
2022-11-01Add the cp15 subsystemAlejandro Soto
2022-11-01Add MUL control cycleAlejandro Soto
2022-11-01Replace decode enable signals with datapath signalsAlejandro Soto
2022-10-31Display undefined instruction messages in simulationAlejandro Soto
2022-10-25Split mux logic out of control.svAlejandro Soto
2022-10-24Split cycle logic out of control.svAlejandro Soto
2022-10-24Split stall control logic out of control.svAlejandro Soto
2022-10-23Move control cycles enum to public uarch interfaceAlejandro Soto
2022-10-23Pack general control signals as struct datapath_decodeAlejandro Soto
2022-10-23Move signal `uses_rn` to struct data_decodeAlejandro Soto
2022-10-23Move branch control signals to struct branch_decodeAlejandro Soto
2022-10-23Fix PC writeback hazardAlejandro Soto
2022-10-23Fix ldm writebackAlejandro Soto
2022-10-18Implement branch with linkAlejandro Soto
2022-10-18Support program counter in --dump-regsAlejandro Soto
2022-10-18Implement undefined instruction exceptionsAlejandro Soto
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