summaryrefslogtreecommitdiff
path: root/rtl/core/control/control.sv
diff options
context:
space:
mode:
authorAlejandro Soto <alejandro@34project.org>2022-11-16 16:46:52 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-16 17:55:27 -0600
commit683352ce030923bdef3cf4fe90d6cb73f4f74529 (patch)
tree09bfdff34626fe90a10d93df2c293f7d87763e44 /rtl/core/control/control.sv
parent14a3611e492d2f213e81c9053bf613a5d8ad30a6 (diff)
Implement psr read/write logic
Diffstat (limited to 'rtl/core/control/control.sv')
-rw-r--r--rtl/core/control/control.sv20
1 files changed, 18 insertions, 2 deletions
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 82aad33..9f398dc 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -8,9 +8,12 @@ module core_control
input insn_decode dec,
input ptr insn_pc,
+ input psr_mode mode,
input psr_flags flags,
alu_flags,
- input word rd_value_a,
+ input word cpsr_rd,
+ spsr_rd,
+ rd_value_a,
rd_value_b,
q_alu,
q_shifter,
@@ -57,7 +60,12 @@ module core_control
mul_long,
mul_start,
mul_signed,
- coproc
+ coproc,
+ psr_saved,
+ psr_write,
+ psr_wr_flags,
+ psr_wr_control,
+ output word psr_wr
);
ctrl_cycle cycle, next_cycle;
@@ -118,6 +126,14 @@ module core_control
.*
);
+ word psr_wb;
+ logic psr, final_psr_write, final_restore_spsr;
+
+ core_control_psr ctrl_psr
+ (
+ .*
+ );
+
logic final_writeback, final_update_flags;
reg_num final_rd;