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AgeCommit message (Collapse)Author
2022-10-17Fix data hazards in nzcv and PC incrementAlejandro Soto
2022-10-16Rename cycles as controlAlejandro Soto
2022-10-15Fix flags and writeback hazardsAlejandro Soto
2022-10-09Implement most memory transactionsAlejandro Soto
2022-10-08Fix writes to PCAlejandro Soto
2022-10-03Fix pipeline hazardsAlejandro Soto
2022-10-02Split decoding of flexible second operand out of data instructionsAlejandro Soto
2022-10-02Make the fetch stage use the bus arbiterAlejandro Soto
2022-10-02Major shifter-ALU redesignAlejandro Soto
The shifter unit now works in parallel with the ALU and is no longer part of it. Instructions that use the shifter as input to the ALU will now take an additional cycle, unless the control unit can detect a "trivial shift" situation where the shifter's output will be the same as its input. This change improves Fmax substantially.
2022-09-27Switch from operand forwarding to next insn stalls (improves Fmax)Alejandro Soto
2022-09-27Implement branching in fetch stageAlejandro Soto
2022-09-26Implement ALU shifterAlejandro Soto
2022-09-25Define ALU control signal setAlejandro Soto
2022-09-25Implement shifter decodingAlejandro Soto
2022-09-25Shorten decode_* nets to dec_*Alejandro Soto
2022-09-25Implement flag updatesAlejandro Soto
2022-09-25Refactor CPSR and uarch.svAlejandro Soto
2022-09-25Implement PSR flag handlingAlejandro Soto
2022-09-25Implement initial cycle control logicAlejandro Soto
2022-09-24Implement initial decoderAlejandro Soto
2022-09-23Implement core stubAlejandro Soto
It only has the fetch stage for now
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