| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-02-20 | rtl: refactor filenames and directory hierarchy | Alejandro Soto |
| 2023-11-16 | rtl/smp: implement SMP dead/alive handling | Alejandro Soto |
| 2023-10-28 | platform: implement support for disabling CPUs | Alejandro Soto |
| 2023-10-02 | rtl/core: implement ldrex/strex decode | Alejandro Soto |
| 2023-10-02 | rtl: implement exclusive monitor datapath | Alejandro Soto |
| 2023-09-30 | platform: implement SMP controller | Alejandro Soto |
| 2023-09-29 | platform: add CPUs and caches to qsys | Alejandro Soto |
| 2023-09-25 | rtl/core, tb: replace bus_master with a new top-level module | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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