diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-10-02 11:15:34 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-10-02 23:29:46 -0600 |
| commit | fbe3ab39675d338eb6d5388b7deacf98a3a8ae2d (patch) | |
| tree | 6a3a8479031d1434a18af4385713dd48207d3814 /core_hw.tcl | |
| parent | 70d7dc9489f4d5b91d8138e0a341eec4ad7f15b0 (diff) | |
rtl/core: implement ldrex/strex decode
Diffstat (limited to 'core_hw.tcl')
| -rw-r--r-- | core_hw.tcl | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/core_hw.tcl b/core_hw.tcl index 9f2d04d..0bdd457 100644 --- a/core_hw.tcl +++ b/core_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 20.1 -# Mon Oct 02 07:41:57 GMT 2023 +# Mon Oct 02 22:54:00 GMT 2023 # DO NOT MODIFY # # core "ARM810 CPU" v1.0 -# 2023.10.02.07:41:57 +# 2023.10.02.22:54:00 # # @@ -105,6 +105,7 @@ add_fileset_file porch.sv SYSTEM_VERILOG PATH rtl/core/porch/porch.sv add_fileset_file file.sv SYSTEM_VERILOG PATH rtl/core/regs/file.sv add_fileset_file reg_map.sv SYSTEM_VERILOG PATH rtl/core/regs/reg_map.sv add_fileset_file regs.sv SYSTEM_VERILOG PATH rtl/core/regs/regs.sv +add_fileset_file exclusive.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/exclusive.sv # |