conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2022-11-16	Implement psr read/write logic	Alejandro Soto
2022-11-15	Implement sub-word memory accesses	Alejandro Soto
2022-11-15	Rename existing MMU components to MMU arbiter	Alejandro Soto
2022-11-15	Replace vga_controller with streaming Altera IP	Alejandro Soto
2022-11-14	Add modified Signal Tap test	Alejandro Soto
2022-11-13	Implement CPU halt	Alejandro Soto
2022-11-13	Add Signal Tap bus master sniffer	Alejandro Soto
2022-11-13	Add reset debounce	Alejandro Soto
2022-11-13	Add debug instrumentation	Alejandro Soto
2022-11-09	Implement initial state randomization in sim	Alejandro Soto
2022-11-08	Add missing toplevel pin connections	Alejandro Soto
2022-11-08	Register decode output in a new porch stage	Alejandro Soto
2022-11-07	Quartus has not support for unique0	Alejandro Soto
2022-11-07	Split decode mux logic out of decode.sv	Alejandro Soto
2022-11-06	Implement decode for mrs, msr	Alejandro Soto
2022-11-06	Move CP15 logic out of control.sv	Alejandro Soto
2022-11-06	Move multiplication logic out of control.sv	Alejandro Soto
2022-11-06	Move load-store logic out of control.sv	Alejandro Soto
2022-11-06	Split regfile read select logic out of control.sv	Alejandro Soto
2022-11-06	Move exception logic out of control.sv	Alejandro Soto
2022-11-06	Split ALU/shifter control logic out of control.sv	Alejandro Soto
2022-11-06	Split branch logic out of control.sv	Alejandro Soto
2022-11-06	Multiplex writeback control signals	Alejandro Soto
2022-11-06	Add dsp_mul IP variation	Alejandro Soto
2022-11-02	Fix qsys memory map	Alejandro Soto
2022-11-01	Add CPUID register	Alejandro Soto
2022-11-01	Add cp15 primary register map	Alejandro Soto
2022-11-01	Add the cp15 subsystem	Alejandro Soto
2022-11-01	Implement coprocessor instruction decode	Alejandro Soto
2022-11-01	Replace decode enable signals with datapath signals	Alejandro Soto
2022-10-31	Move mul.sv to rtl/core	Alejandro Soto
2022-10-25	Split mux logic out of control.sv	Alejandro Soto
2022-10-17	Break sub-100MHz critical path involving wb_alu_flags	Alejandro Soto
2022-10-16	Rename cycles as control	Alejandro Soto
2022-10-16	Move isa.sv to core/decode	Alejandro Soto
2022-10-15	Rework bus architecture	Alejandro Soto
2022-10-08	Implement LDR/STR decode	Alejandro Soto
2022-10-02	Split decoding of flexible second operand out of data instructions	Alejandro Soto
2022-10-02	Make the fetch stage use the bus arbiter	Alejandro Soto
2022-10-02	Major shifter-ALU redesign	Alejandro Soto
2022-09-25	Fix Quartus issues	Alejandro Soto
2022-09-23	Add toplevel module for core tests	Alejandro Soto
2022-09-19	DDR3 is working	Alejandro Soto
2022-09-18	Rename data_rw to data_wr in bus master	Alejandro Soto
2022-09-17	Update project structure to match Verilator Makefile	Alejandro Soto
2022-09-04	Add SDRAM test	Alejandro Soto
2022-09-02	Fix output buffer atom errors	Alejandro Soto
2022-09-02	Add hps_0 platform design	Alejandro Soto
2022-09-01	Initial commit	Alejandro Soto