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authorAlejandro Soto <alejandro@34project.org>2022-10-02 09:49:48 -0600
committerAlejandro Soto <alejandro@34project.org>2022-10-02 09:49:48 -0600
commite97d445908f39a3a1a215a824f52b283147e6195 (patch)
tree74baa4d5ee535c12dbbe400f8e6c2fda342b8e37 /conspiracion.qsf
parent5e2f6be247018699d71d32887010830ba45b8349 (diff)
Major shifter-ALU redesign
The shifter unit now works in parallel with the ALU and is no longer part of it. Instructions that use the shifter as input to the ALU will now take an additional cycle, unless the control unit can detect a "trivial shift" situation where the shifter's output will be the same as its input. This change improves Fmax substantially.
Diffstat (limited to 'conspiracion.qsf')
-rw-r--r--conspiracion.qsf2
1 files changed, 2 insertions, 0 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf
index c81ea0a..e8371d3 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -226,6 +226,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/xor.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/add.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/alu.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/psr.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/shifter.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/file.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/regs.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/map.sv
@@ -240,4 +241,5 @@ set_global_assignment -name QIP_FILE platform/synthesis/platform.qip
set_global_assignment -name SDC_FILE conspiracion.sdc
+
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file