conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2024-04-27	target/de1soc: move quartus files out of project root	Alejandro Soto
2023-11-22	rtl/gfx: implement primitive assembly	Alejandro Soto
2023-11-22	rtl/gfx: implement fp->fixed conversion	Alejandro Soto
2023-11-20	rtl/gfx: remove gfx_{perspective{,_flow}, fp_inv}	Alejandro Soto
2023-11-10	rtl/gfx: implement fixed-point FMA	Alejandro Soto
2023-11-02	ip: add ip_fp_inv	Alejandro Soto
2023-10-26	rtl/gfx: synchronize clock with SDRAM	Alejandro Soto
2023-10-20	ip: add ip_fp_add, ip_fp_mul	Alejandro Soto
2023-09-30	platform: implement SMP controller	Alejandro Soto
2023-09-29	qsf: enable ModelSim-Altera	Alejandro Soto
2023-09-25	rtl/core, tb: replace bus_master with a new top-level module	Alejandro Soto
2022-12-16	Add interrupt controller to Platform Designer	Alejandro Soto
2022-12-16	Add cp15 cyclecnt clock source	Alejandro Soto
2022-12-16	Implement MMU access checks	Alejandro Soto
2022-12-16	Implement hardware virtual memory	Alejandro Soto
2022-12-10	Implement rest of cp15 registers	Alejandro Soto
2022-12-07	Implement single-stepping	Alejandro Soto
2022-11-17	Bug fixes	JulianCamacho
2022-11-16	Fix carry flag bug	Alejandro Soto
2022-11-16	Implement psr read/write logic	Alejandro Soto
2022-11-15	Implement sub-word memory accesses	Alejandro Soto
2022-11-15	Rename existing MMU components to MMU arbiter	Alejandro Soto
2022-11-15	Replace vga_controller with streaming Altera IP	Alejandro Soto
2022-11-14	Add modified Signal Tap test	Alejandro Soto
2022-11-13	Implement CPU halt	Alejandro Soto
2022-11-13	Add Signal Tap bus master sniffer	Alejandro Soto
2022-11-13	Add reset debounce	Alejandro Soto
2022-11-13	Add debug instrumentation	Alejandro Soto
2022-11-09	Implement initial state randomization in sim	Alejandro Soto
2022-11-08	Add missing toplevel pin connections	Alejandro Soto
2022-11-08	Register decode output in a new porch stage	Alejandro Soto
2022-11-07	Quartus has not support for unique0	Alejandro Soto
2022-11-07	Split decode mux logic out of decode.sv	Alejandro Soto
2022-11-06	Implement decode for mrs, msr	Alejandro Soto
2022-11-06	Move CP15 logic out of control.sv	Alejandro Soto
2022-11-06	Move multiplication logic out of control.sv	Alejandro Soto
2022-11-06	Move load-store logic out of control.sv	Alejandro Soto
2022-11-06	Split regfile read select logic out of control.sv	Alejandro Soto
2022-11-06	Move exception logic out of control.sv	Alejandro Soto
2022-11-06	Split ALU/shifter control logic out of control.sv	Alejandro Soto
2022-11-06	Split branch logic out of control.sv	Alejandro Soto
2022-11-06	Multiplex writeback control signals	Alejandro Soto
2022-11-06	Add dsp_mul IP variation	Alejandro Soto
2022-11-02	Fix qsys memory map	Alejandro Soto
2022-11-01	Add CPUID register	Alejandro Soto
2022-11-01	Add cp15 primary register map	Alejandro Soto
2022-11-01	Add the cp15 subsystem	Alejandro Soto
2022-11-01	Implement coprocessor instruction decode	Alejandro Soto
2022-11-01	Replace decode enable signals with datapath signals	Alejandro Soto
2022-10-31	Move mul.sv to rtl/core	Alejandro Soto