diff options
| author | Alejandro Soto <alejandro@34project.org> | 2024-05-05 18:45:11 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-05-05 18:45:11 -0600 |
| commit | 638b75fb4c8fdc3c9d3a208f6bd9976841bc0928 (patch) | |
| tree | 3f26dad5958d6713d942b53b8c0bf62e003565a3 /rtl/if_common/if_axil2regblock.sv | |
| parent | 1ffcdb62cd7e95ccd3f971d0b5cb2e617e1481b2 (diff) | |
rtl/if_common: initial commit, moved out of gfx
Diffstat (limited to 'rtl/if_common/if_axil2regblock.sv')
| -rw-r--r-- | rtl/if_common/if_axil2regblock.sv | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/rtl/if_common/if_axil2regblock.sv b/rtl/if_common/if_axil2regblock.sv new file mode 100644 index 0000000..d3c20d9 --- /dev/null +++ b/rtl/if_common/if_axil2regblock.sv @@ -0,0 +1,30 @@ +module if_axil2regblock +( + if_axil.s axis, + axi4lite_intf.master axim +); + + assign axis.rdata = axim.RDATA; + assign axis.rvalid = axim.RVALID; + assign axis.bvalid = axim.BVALID; + assign axis.wready = axim.WREADY; + assign axis.arready = axim.ARREADY; + assign axis.awready = axim.AWREADY; + + assign axim.AWVALID = axis.awvalid; + assign axim.AWADDR = axis.awaddr[$bits(axim.AWADDR) - 1:0]; + assign axim.AWPROT = '0; + + assign axim.WVALID = axis.wvalid; + assign axim.WDATA = axis.wdata; + assign axim.WSTRB = '1; + + assign axim.BREADY = axis.bready; + + assign axim.ARVALID = axis.arvalid; + assign axim.ARADDR = axis.araddr[$bits(axim.ARADDR) - 1:0]; + assign axim.ARPROT = '0; + + assign axim.RREADY = axis.rready; + +endmodule |
