From 638b75fb4c8fdc3c9d3a208f6bd9976841bc0928 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 5 May 2024 18:45:11 -0600 Subject: rtl/if_common: initial commit, moved out of gfx --- rtl/if_common/if_axil2regblock.sv | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 rtl/if_common/if_axil2regblock.sv (limited to 'rtl/if_common/if_axil2regblock.sv') diff --git a/rtl/if_common/if_axil2regblock.sv b/rtl/if_common/if_axil2regblock.sv new file mode 100644 index 0000000..d3c20d9 --- /dev/null +++ b/rtl/if_common/if_axil2regblock.sv @@ -0,0 +1,30 @@ +module if_axil2regblock +( + if_axil.s axis, + axi4lite_intf.master axim +); + + assign axis.rdata = axim.RDATA; + assign axis.rvalid = axim.RVALID; + assign axis.bvalid = axim.BVALID; + assign axis.wready = axim.WREADY; + assign axis.arready = axim.ARREADY; + assign axis.awready = axim.AWREADY; + + assign axim.AWVALID = axis.awvalid; + assign axim.AWADDR = axis.awaddr[$bits(axim.AWADDR) - 1:0]; + assign axim.AWPROT = '0; + + assign axim.WVALID = axis.wvalid; + assign axim.WDATA = axis.wdata; + assign axim.WSTRB = '1; + + assign axim.BREADY = axis.bready; + + assign axim.ARVALID = axis.arvalid; + assign axim.ARADDR = axis.araddr[$bits(axim.ARADDR) - 1:0]; + assign axim.ARPROT = '0; + + assign axim.RREADY = axis.rready; + +endmodule -- cgit v1.2.3