rtl/if_common: initial commit, moved out of gfx

7 files changed, 254 insertions, 0 deletions

diff --git a/rtl/if_common/if_axib.sv b/rtl/if_common/if_axib.sv
new file mode 100644
index 0000000..6db8518
--- /dev/null
+++ b/rtl/if_common/if_axib.sv
@@ -0,0 +1,80 @@
+// AXI4 con burst
+interface if_axib
+#(int WIDTH = 32);
+
+	logic              awvalid,
+	                   awready;
+	logic[7:0]         awlen;
+	logic[1:0]         awburst;
+	logic[WIDTH - 1:0] awaddr;
+
+	logic              wlast;
+	logic              wvalid;
+	logic              wready;
+	logic[WIDTH - 1:0] wdata;
+
+	logic bvalid;
+	logic bready;
+
+	logic              arvalid,
+	                   arready;
+	logic[7:0]         arlen;
+	logic[1:0]         arburst;
+	logic[WIDTH - 1:0] araddr;
+
+	logic              rlast;
+	logic              rvalid;
+	logic              rready;
+	logic[WIDTH - 1:0] rdata;
+
+	modport m
+	(
+		input  awready,
+		       wready,
+		       bvalid,
+		       arready,
+		       rlast,
+		       rvalid,
+		       rdata,
+
+		output awlen,
+		       awburst,
+		       awvalid,
+		       awaddr,
+		       wlast,
+		       wvalid,
+		       wdata,
+		       bready,
+		       arlen,
+		       arburst,
+		       arvalid,
+		       araddr,
+		       rready
+	);
+
+	modport s
+	(
+		input  awlen,
+		       awburst,
+		       awvalid,
+		       awaddr,
+		       wlast,
+		       wvalid,
+		       wdata,
+		       bready,
+		       arlen,
+		       arburst,
+		       arvalid,
+		       araddr,
+		       rready,
+
+		output awready,
+		       wready,
+		       bvalid,
+		       arready,
+		       rlast,
+		       rvalid,
+		       rdata
+	);
+
+endinterface
diff --git a/rtl/if_common/if_axil.sv b/rtl/if_common/if_axil.sv
new file mode 100644
index 0000000..cf67e3f
--- /dev/null
+++ b/rtl/if_common/if_axil.sv
@@ -0,0 +1,61 @@
+// AXI4-Lite, sin wstrb ni axprot
+interface if_axil
+#(int WIDTH = 32);
+
+	logic              awvalid;
+	logic              awready;
+	logic[WIDTH - 1:0] awaddr;
+
+	logic              wvalid;
+	logic              wready;
+	logic[WIDTH - 1:0] wdata;
+
+	logic bvalid;
+	logic bready;
+
+	logic              arvalid;
+	logic              arready;
+	logic[WIDTH - 1:0] araddr;
+
+	logic              rvalid;
+	logic              rready;
+	logic[WIDTH - 1:0] rdata;
+
+	modport m
+	(
+		input  awready,
+		       wready,
+		       bvalid,
+		       arready,
+		       rvalid,
+		       rdata,
+
+		output awvalid,
+		       awaddr,
+		       wvalid,
+		       wdata,
+		       bready,
+		       arvalid,
+		       araddr,
+		       rready
+	);
+
+	modport s
+	(
+		input  awvalid,
+		       awaddr,
+		       wvalid,
+		       wdata,
+		       bready,
+		       arvalid,
+		       araddr,
+		       rready,
+
+		output awready,
+		       wready,
+		       bvalid,
+		       arready,
+		       rvalid,
+		       rdata
+	);
+endinterface
diff --git a/rtl/if_common/if_axil2regblock.sv b/rtl/if_common/if_axil2regblock.sv
new file mode 100644
index 0000000..d3c20d9
--- /dev/null
+++ b/rtl/if_common/if_axil2regblock.sv
@@ -0,0 +1,30 @@
+module if_axil2regblock
+(
+	if_axil.s            axis,
+	axi4lite_intf.master axim
+);
+
+	assign axis.rdata = axim.RDATA;
+	assign axis.rvalid = axim.RVALID;
+	assign axis.bvalid = axim.BVALID;
+	assign axis.wready = axim.WREADY;
+	assign axis.arready = axim.ARREADY;
+	assign axis.awready = axim.AWREADY;
+
+    assign axim.AWVALID = axis.awvalid;
+    assign axim.AWADDR = axis.awaddr[$bits(axim.AWADDR) - 1:0];
+    assign axim.AWPROT = '0;
+
+    assign axim.WVALID = axis.wvalid;
+    assign axim.WDATA = axis.wdata;
+    assign axim.WSTRB = '1;
+
+    assign axim.BREADY = axis.bready;
+
+    assign axim.ARVALID = axis.arvalid;
+    assign axim.ARADDR = axis.araddr[$bits(axim.ARADDR) - 1:0];
+    assign axim.ARPROT = '0;
+
+    assign axim.RREADY = axis.rready;
+
+endmodule
diff --git a/rtl/if_common/if_beats.sv b/rtl/if_common/if_beats.sv
new file mode 100644
index 0000000..f9e58e9
--- /dev/null
+++ b/rtl/if_common/if_beats.sv
@@ -0,0 +1,29 @@
+interface if_beats
+#(int WIDTH = 32);
+
+	logic[WIDTH - 1:0] data;
+	logic              ready;
+	logic              valid;
+
+	modport tx
+	(
+		input  ready,
+		output data,
+		       valid
+	);
+
+	modport rx
+	(
+		input  data,
+		       valid,
+		output ready
+	);
+
+	modport peek
+	(
+		input  data,
+		       ready,
+		       valid
+	);
+
+endinterface
diff --git a/rtl/if_common/if_pkts.sv b/rtl/if_common/if_pkts.sv
new file mode 100644
index 0000000..b6e5b0b
--- /dev/null
+++ b/rtl/if_common/if_pkts.sv
@@ -0,0 +1,27 @@
+interface if_pkts
+#(int WIDTH = 32);
+
+	logic              tlast;
+	logic              tready;
+	logic              tvalid;
+	logic[WIDTH - 1:0] tdata;
+
+	modport tx
+	(
+		input  tready,
+
+		output tdata,
+			   tlast,
+			   tvalid
+	);
+
+	modport rx
+	(
+		input  tdata,
+			   tlast,
+			   tvalid,
+
+		output tready
+	);
+
+endinterface
diff --git a/rtl/if_common/if_shake.sv b/rtl/if_common/if_shake.sv
new file mode 100644
index 0000000..8ec5a73
--- /dev/null
+++ b/rtl/if_common/if_shake.sv
@@ -0,0 +1,24 @@
+interface if_shake;
+
+	logic ready;
+	logic valid;
+
+	modport tx
+	(
+		input  ready,
+		output valid
+	);
+
+	modport rx
+	(
+		input  valid,
+		output ready
+	);
+
+	modport peek
+	(
+		input  ready,
+		       valid
+	);
+
+endinterface
diff --git a/rtl/if_common/mod.mk b/rtl/if_common/mod.mk
new file mode 100644
index 0000000..e60abc4
--- /dev/null
+++ b/rtl/if_common/mod.mk
@@ -0,0 +1,3 @@
+define core
+  $(this)/rtl_dirs := .
+endef