rtl: refactor filenames and directory hierarchy

3 files changed, 0 insertions, 150 deletions

diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv
deleted file mode 100644
index 2ba95e8..0000000
--- a/rtl/core/regs/file.sv
+++ /dev/null
@@ -1,51 +0,0 @@
-`include "core/uarch.sv"
-
-module core_reg_file
-(
-	input  logic     clk,
-	                 rst_n,
-
-	input  psr_mode  rd_mode,
-	input  reg_num   rd_r,
-	input  reg_index wr_index,
-	input  logic     wr_enable,
-	                 wr_enable_file,
-	input  word      wr_value,
-	                 wr_current,
-	                 pc_word,
-
-	output word      rd_value
-);
-
-	// Ver comentario en uarch.sv
-	word file[`NUM_GPREGS] /*verilator public*/;
-	word rd_actual;
-	logic rd_pc, hold_rd_pc, forward;
-	reg_index rd_index;
-
-	core_reg_map map_rd
-	(
-		.r(rd_r),
-		.mode(rd_mode),
-		.is_pc(rd_pc),
-		.index(rd_index)
-	);
-
-	assign rd_value = hold_rd_pc ? pc_word : forward ? wr_current : rd_actual;
-
-	always_ff @(posedge clk or negedge rst_n)
-		if(!rst_n) begin
-			forward <= 0;
-			rd_actual <= 0;
-			hold_rd_pc <= 0;
-		end else begin
-			forward <= wr_enable && rd_index == wr_index;
-			hold_rd_pc <= rd_pc;
-
-			if(wr_enable_file)
-				file[wr_index] <= wr_value;
-
-			rd_actual <= file[rd_index];
-		end
-
-endmodule
diff --git a/rtl/core/regs/reg_map.sv b/rtl/core/regs/reg_map.sv
deleted file mode 100644
index 11085d4..0000000
--- a/rtl/core/regs/reg_map.sv
+++ /dev/null
@@ -1,30 +0,0 @@
-`include "core/uarch.sv"
-
-module core_reg_map
-(
-	input  reg_num   r,
-	input  psr_mode  mode,
-	output logic     is_pc,
-	output reg_index index
-);
-
-	reg_index usr;
-	assign usr = {1'b0, r};
-
-	always_comb begin
-		index = 5'bxxxxx;
-		is_pc = r == `R15;
-
-		if(~is_pc)
-			unique case(mode)
-				`MODE_USR, `MODE_SYS: index = usr;
-				`MODE_FIQ: index = r >=  8 ? usr +  7 : usr;
-				`MODE_IRQ: index = r >= 13 ? usr +  9 : usr;
-				`MODE_UND: index = r >= 13 ? usr + 11 : usr;
-				`MODE_ABT: index = r >= 13 ? usr + 13 : usr;
-				`MODE_SVC: index = r >= 13 ? usr + 15 : usr;
-				default: ;
-			endcase
-	end
-
-endmodule
diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv
deleted file mode 100644
index f9cecad..0000000
--- a/rtl/core/regs/regs.sv
+++ /dev/null
@@ -1,69 +0,0 @@
-`include "core/uarch.sv"
-
-module core_regs
-(
-	input  logic    clk,
-	                rst_n,
-
-	input  reg_num  rd_r_a,
-	                rd_r_b,
-	                wr_r,
-	input  psr_mode rd_mode,
-	                wr_mode,
-	input  logic    wr_enable,
-	input  word     wr_value,
-	input  ptr      pc_visible,
-
-	output word     rd_value_a,
-	                rd_value_b,
-	                wr_current,
-	output logic    branch
-);
-
-	/* Las Cyclone V no tienen bloques de memoria con al menos dos puertos de
-	 * lectura y uno de escritura (tres puertos), lo más que tienen son bloques
-	 * de dos puertos en total. Podemos ponerle cinta a esto con dos copias
-	 * sincronizadas del archivo de registros.
-	 */
-
-	word pc_word;
-	logic wr_pc, wr_enable_file;
-	reg_index wr_index;
-
-	assign pc_word = {pc_visible, 2'b00};
-	assign wr_enable_file = wr_enable && !wr_pc;
-
-	core_reg_file a
-	(
-		.rd_r(rd_r_a),
-		.rd_value(rd_value_a),
-		.*
-	);
-
-	core_reg_file b
-	(
-		.rd_r(rd_r_b),
-		.rd_value(rd_value_b),
-		.*
-	);
-
-	core_reg_map map_wr
-	(
-		.r(wr_r),
-		.mode(wr_mode),
-		.is_pc(wr_pc),
-		.index(wr_index)
-	);
-
-	always_ff @(posedge clk or negedge rst_n)
-		if(!rst_n) begin
-			branch <= 0;
-			wr_current <= 0;
-		end else begin
-			if(wr_enable)
-				wr_current <= wr_value;
-
-			branch <= wr_enable && wr_pc;
-		end
-
-endmodule