rtl: refactor filenames and directory hierarchy

79 files changed, 105 insertions, 105 deletions

diff --git a/cache_hw.tcl b/cache_hw.tcl
index 712cf67..57b68e6 100644
--- a/cache_hw.tcl
+++ b/cache_hw.tcl
@@ -39,16 +39,16 @@ add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
 set_fileset_property QUARTUS_SYNTH TOP_LEVEL cache
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file defs.sv SYSTEM_VERILOG PATH rtl/cache/defs.sv
 add_fileset_file cache.sv SYSTEM_VERILOG PATH rtl/cache/cache.sv TOP_LEVEL_FILE
 add_fileset_file cache_control.sv SYSTEM_VERILOG PATH rtl/cache/cache_control.sv
-add_fileset_file token.sv SYSTEM_VERILOG PATH rtl/cache/token.sv
-add_fileset_file ring.sv SYSTEM_VERILOG PATH rtl/cache/ring.sv
-add_fileset_file mem.sv SYSTEM_VERILOG PATH rtl/cache/mem.sv
-add_fileset_file defs.sv SYSTEM_VERILOG PATH rtl/cache/defs.sv
-add_fileset_file offsets.sv SYSTEM_VERILOG PATH rtl/cache/offsets.sv
-add_fileset_file routing.sv SYSTEM_VERILOG PATH rtl/cache/routing.sv
-add_fileset_file sram.sv SYSTEM_VERILOG PATH rtl/cache/sram.sv
-add_fileset_file monitor.sv SYSTEM_VERILOG PATH rtl/cache/monitor.sv
+add_fileset_file cache_token.sv SYSTEM_VERILOG PATH rtl/cache/cache_token.sv
+add_fileset_file cache_ring.sv SYSTEM_VERILOG PATH rtl/cache/cache_ring.sv
+add_fileset_file cache_mem.sv SYSTEM_VERILOG PATH rtl/cache/cache_mem.sv
+add_fileset_file cache_offsets.sv SYSTEM_VERILOG PATH rtl/cache/cache_offsets.sv
+add_fileset_file cache_routing.sv SYSTEM_VERILOG PATH rtl/cache/cache_routing.sv
+add_fileset_file cache_sram.sv SYSTEM_VERILOG PATH rtl/cache/cache_sram.sv
+add_fileset_file cache_monitor.sv SYSTEM_VERILOG PATH rtl/cache/cache_monitor.sv
 add_fileset_file cache_debug.sv SYSTEM_VERILOG PATH rtl/cache/cache_debug.sv
 
 
diff --git a/core_hw.tcl b/core_hw.tcl
index 65d0e99..ed82b8f 100644
--- a/core_hw.tcl
+++ b/core_hw.tcl
@@ -39,74 +39,74 @@ add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
 set_fileset_property QUARTUS_SYNTH TOP_LEVEL core
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file core.sv SYSTEM_VERILOG PATH rtl/core/core.sv TOP_LEVEL_FILE
-add_fileset_file bus_master.sv SYSTEM_VERILOG PATH rtl/core/bus_master.sv
 add_fileset_file arm810.sv SYSTEM_VERILOG PATH rtl/core/arm810.sv
-add_fileset_file mul.sv SYSTEM_VERILOG PATH rtl/core/mul.sv
-add_fileset_file psr.sv SYSTEM_VERILOG PATH rtl/core/psr.sv
-add_fileset_file shifter.sv SYSTEM_VERILOG PATH rtl/core/shifter.sv
+add_fileset_file bus_master.sv SYSTEM_VERILOG PATH rtl/core/bus_master.sv
+add_fileset_file core.sv SYSTEM_VERILOG PATH rtl/core/core.sv TOP_LEVEL_FILE
+add_fileset_file core_alu.sv SYSTEM_VERILOG PATH rtl/core/core_alu.sv
+add_fileset_file core_alu_add.sv SYSTEM_VERILOG PATH rtl/core/core_alu_add.sv
+add_fileset_file core_alu_and.sv SYSTEM_VERILOG PATH rtl/core/core_alu_and.sv
+add_fileset_file core_alu_orr.sv SYSTEM_VERILOG PATH rtl/core/core_alu_orr.sv
+add_fileset_file core_alu_xor.sv SYSTEM_VERILOG PATH rtl/core/core_alu_xor.sv
+add_fileset_file core_control.sv SYSTEM_VERILOG PATH rtl/core/core_control.sv
+add_fileset_file core_control_branch.sv SYSTEM_VERILOG PATH rtl/core/core_control_branch.sv
+add_fileset_file core_control_coproc.sv SYSTEM_VERILOG PATH rtl/core/core_control_coproc.sv
+add_fileset_file core_control_cycles.sv SYSTEM_VERILOG PATH rtl/core/core_control_cycles.sv
+add_fileset_file core_control_data.sv SYSTEM_VERILOG PATH rtl/core/core_control_data.sv
+add_fileset_file core_control_debug.sv SYSTEM_VERILOG PATH rtl/core/core_control_debug.sv
+add_fileset_file core_control_exception.sv SYSTEM_VERILOG PATH rtl/core/core_control_exception.sv
+add_fileset_file core_control_issue.sv SYSTEM_VERILOG PATH rtl/core/core_control_issue.sv
+add_fileset_file core_control_ldst.sv SYSTEM_VERILOG PATH rtl/core/core_control_ldst.sv
+add_fileset_file core_control_ldst_pop.sv SYSTEM_VERILOG PATH rtl/core/core_control_ldst_pop.sv
+add_fileset_file core_control_ldst_sizes.sv SYSTEM_VERILOG PATH rtl/core/core_control_ldst_sizes.sv
+add_fileset_file core_control_mul.sv SYSTEM_VERILOG PATH rtl/core/core_control_mul.sv
+add_fileset_file core_control_psr.sv SYSTEM_VERILOG PATH rtl/core/core_control_psr.sv
+add_fileset_file core_control_select.sv SYSTEM_VERILOG PATH rtl/core/core_control_select.sv
+add_fileset_file core_control_stall.sv SYSTEM_VERILOG PATH rtl/core/core_control_stall.sv
+add_fileset_file core_control_writeback.sv SYSTEM_VERILOG PATH rtl/core/core_control_writeback.sv
+add_fileset_file core_cp15.sv SYSTEM_VERILOG PATH rtl/core/core_cp15.sv
+add_fileset_file core_cp15_cache.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_cache.sv
+add_fileset_file core_cp15_cache_lockdown.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_cache_lockdown.sv
+add_fileset_file core_cp15_cpuid.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_cpuid.sv
+add_fileset_file core_cp15_cyclecnt.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_cyclecnt.sv
+add_fileset_file core_cp15_domain.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_domain.sv
+add_fileset_file core_cp15_far.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_far.sv
+add_fileset_file core_cp15_fsr.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_fsr.sv
+add_fileset_file core_cp15_syscfg.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_syscfg.sv
+add_fileset_file core_cp15_tlb.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_tlb.sv
+add_fileset_file core_cp15_tlb_lockdown.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_tlb_lockdown.sv
+add_fileset_file core_cp15_ttbr.sv SYSTEM_VERILOG PATH rtl/core/core_cp15_ttbr.sv
+add_fileset_file core_decode.sv SYSTEM_VERILOG PATH rtl/core/core_decode.sv
+add_fileset_file core_decode_branch.sv SYSTEM_VERILOG PATH rtl/core/core_decode_branch.sv
+add_fileset_file core_decode_coproc.sv SYSTEM_VERILOG PATH rtl/core/core_decode_coproc.sv
+add_fileset_file core_decode_data.sv SYSTEM_VERILOG PATH rtl/core/core_decode_data.sv
+add_fileset_file core_decode_ldst_addr.sv SYSTEM_VERILOG PATH rtl/core/core_decode_ldst_addr.sv
+add_fileset_file core_decode_ldst_exclusive.sv SYSTEM_VERILOG PATH rtl/core/core_decode_ldst_exclusive.sv
+add_fileset_file core_decode_ldst_misc.sv SYSTEM_VERILOG PATH rtl/core/core_decode_ldst_misc.sv
+add_fileset_file core_decode_ldst_multiple.sv SYSTEM_VERILOG PATH rtl/core/core_decode_ldst_multiple.sv
+add_fileset_file core_decode_ldst_single.sv SYSTEM_VERILOG PATH rtl/core/core_decode_ldst_single.sv
+add_fileset_file core_decode_mrs.sv SYSTEM_VERILOG PATH rtl/core/core_decode_mrs.sv
+add_fileset_file core_decode_msr.sv SYSTEM_VERILOG PATH rtl/core/core_decode_msr.sv
+add_fileset_file core_decode_mul.sv SYSTEM_VERILOG PATH rtl/core/core_decode_mul.sv
+add_fileset_file core_decode_mux.sv SYSTEM_VERILOG PATH rtl/core/core_decode_mux.sv
+add_fileset_file core_decode_snd.sv SYSTEM_VERILOG PATH rtl/core/core_decode_snd.sv
+add_fileset_file core_fetch.sv SYSTEM_VERILOG PATH rtl/core/core_fetch.sv
+add_fileset_file core_mmu.sv SYSTEM_VERILOG PATH rtl/core/core_mmu.sv
+add_fileset_file core_mmu_arbiter.sv SYSTEM_VERILOG PATH rtl/core/core_mmu_arbiter.sv
+add_fileset_file core_mmu_fault.sv SYSTEM_VERILOG PATH rtl/core/core_mmu_fault.sv
+add_fileset_file core_mmu_pagewalk.sv SYSTEM_VERILOG PATH rtl/core/core_mmu_pagewalk.sv
+add_fileset_file core_mul.sv SYSTEM_VERILOG PATH rtl/core/core_mul.sv
+add_fileset_file core_porch.sv SYSTEM_VERILOG PATH rtl/core/core_porch.sv
+add_fileset_file core_porch_conds.sv SYSTEM_VERILOG PATH rtl/core/core_porch_conds.sv
+add_fileset_file core_prefetch.sv SYSTEM_VERILOG PATH rtl/core/core_prefetch.sv
+add_fileset_file core_psr.sv SYSTEM_VERILOG PATH rtl/core/core_psr.sv
+add_fileset_file core_reg_file.sv SYSTEM_VERILOG PATH rtl/core/core_reg_file.sv
+add_fileset_file core_reg_map.sv SYSTEM_VERILOG PATH rtl/core/core_reg_map.sv
+add_fileset_file core_regs.sv SYSTEM_VERILOG PATH rtl/core/core_regs.sv
+add_fileset_file core_shifter.sv SYSTEM_VERILOG PATH rtl/core/core_shifter.sv
+add_fileset_file cp15_map.sv SYSTEM_VERILOG PATH rtl/core/cp15_map.sv
+add_fileset_file isa.sv SYSTEM_VERILOG PATH rtl/core/isa.sv
+add_fileset_file mmu_format.sv SYSTEM_VERILOG PATH rtl/core/mmu_format.sv
 add_fileset_file uarch.sv SYSTEM_VERILOG PATH rtl/core/uarch.sv
-add_fileset_file add.sv SYSTEM_VERILOG PATH rtl/core/alu/add.sv
-add_fileset_file alu.sv SYSTEM_VERILOG PATH rtl/core/alu/alu.sv
-add_fileset_file and.sv SYSTEM_VERILOG PATH rtl/core/alu/and.sv
-add_fileset_file orr.sv SYSTEM_VERILOG PATH rtl/core/alu/orr.sv
-add_fileset_file xor.sv SYSTEM_VERILOG PATH rtl/core/alu/xor.sv
-add_fileset_file branch.sv SYSTEM_VERILOG PATH rtl/core/control/branch.sv
-add_fileset_file control.sv SYSTEM_VERILOG PATH rtl/core/control/control.sv
-add_fileset_file coproc.sv SYSTEM_VERILOG PATH rtl/core/control/coproc.sv
-add_fileset_file cycles.sv SYSTEM_VERILOG PATH rtl/core/control/cycles.sv
-add_fileset_file data.sv SYSTEM_VERILOG PATH rtl/core/control/data.sv
-add_fileset_file debug.sv SYSTEM_VERILOG PATH rtl/core/control/debug.sv
-add_fileset_file exception.sv SYSTEM_VERILOG PATH rtl/core/control/exception.sv
-add_fileset_file issue.sv SYSTEM_VERILOG PATH rtl/core/control/issue.sv
-add_fileset_file mul_fu.sv SYSTEM_VERILOG PATH rtl/core/control/mul_fu.sv
-add_fileset_file select.sv SYSTEM_VERILOG PATH rtl/core/control/select.sv
-add_fileset_file stall.sv SYSTEM_VERILOG PATH rtl/core/control/stall.sv
-add_fileset_file status.sv SYSTEM_VERILOG PATH rtl/core/control/status.sv
-add_fileset_file writeback.sv SYSTEM_VERILOG PATH rtl/core/control/writeback.sv
-add_fileset_file ldst.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/ldst.sv
-add_fileset_file pop.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/pop.sv
-add_fileset_file sizes.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/sizes.sv
-add_fileset_file cache_ops.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache_ops.sv
-add_fileset_file cache_lockdown.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache_lockdown.sv
-add_fileset_file cp15.sv SYSTEM_VERILOG PATH rtl/core/cp15/cp15.sv
-add_fileset_file cpuid.sv SYSTEM_VERILOG PATH rtl/core/cp15/cpuid.sv
-add_fileset_file cyclecnt.sv SYSTEM_VERILOG PATH rtl/core/cp15/cyclecnt.sv
-add_fileset_file domain.sv SYSTEM_VERILOG PATH rtl/core/cp15/domain.sv
-add_fileset_file far.sv SYSTEM_VERILOG PATH rtl/core/cp15/far.sv
-add_fileset_file fsr.sv SYSTEM_VERILOG PATH rtl/core/cp15/fsr.sv
-add_fileset_file map.sv SYSTEM_VERILOG PATH rtl/core/cp15/map.sv
-add_fileset_file syscfg.sv SYSTEM_VERILOG PATH rtl/core/cp15/syscfg.sv
-add_fileset_file tlb.sv SYSTEM_VERILOG PATH rtl/core/cp15/tlb.sv
-add_fileset_file tlb_lockdown.sv SYSTEM_VERILOG PATH rtl/core/cp15/tlb_lockdown.sv
-add_fileset_file ttbr.sv SYSTEM_VERILOG PATH rtl/core/cp15/ttbr.sv
-add_fileset_file branch_dec.sv SYSTEM_VERILOG PATH rtl/core/decode/branch_dec.sv
-add_fileset_file coproc_dec.sv SYSTEM_VERILOG PATH rtl/core/decode/coproc_dec.sv
-add_fileset_file data_dec.sv SYSTEM_VERILOG PATH rtl/core/decode/data_dec.sv
-add_fileset_file decode.sv SYSTEM_VERILOG PATH rtl/core/decode/decode.sv
-add_fileset_file isa.sv SYSTEM_VERILOG PATH rtl/core/decode/isa.sv
-add_fileset_file mrs.sv SYSTEM_VERILOG PATH rtl/core/decode/mrs.sv
-add_fileset_file msr.sv SYSTEM_VERILOG PATH rtl/core/decode/msr.sv
-add_fileset_file mul_dec.sv SYSTEM_VERILOG PATH rtl/core/decode/mul_dec.sv
-add_fileset_file mux.sv SYSTEM_VERILOG PATH rtl/core/decode/mux.sv
-add_fileset_file snd.sv SYSTEM_VERILOG PATH rtl/core/decode/snd.sv
-add_fileset_file addr.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/addr.sv
-add_fileset_file misc.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/misc.sv
-add_fileset_file multiple.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/multiple.sv
-add_fileset_file single.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/single.sv
-add_fileset_file fetch.sv SYSTEM_VERILOG PATH rtl/core/fetch/fetch.sv
-add_fileset_file prefetch.sv SYSTEM_VERILOG PATH rtl/core/fetch/prefetch.sv
-add_fileset_file arbiter.sv SYSTEM_VERILOG PATH rtl/core/mmu/arbiter.sv
-add_fileset_file fault.sv SYSTEM_VERILOG PATH rtl/core/mmu/fault.sv
-add_fileset_file format.sv SYSTEM_VERILOG PATH rtl/core/mmu/format.sv
-add_fileset_file mmu.sv SYSTEM_VERILOG PATH rtl/core/mmu/mmu.sv
-add_fileset_file pagewalk.sv SYSTEM_VERILOG PATH rtl/core/mmu/pagewalk.sv
-add_fileset_file conds.sv SYSTEM_VERILOG PATH rtl/core/porch/conds.sv
-add_fileset_file porch.sv SYSTEM_VERILOG PATH rtl/core/porch/porch.sv
-add_fileset_file file.sv SYSTEM_VERILOG PATH rtl/core/regs/file.sv
-add_fileset_file reg_map.sv SYSTEM_VERILOG PATH rtl/core/regs/reg_map.sv
-add_fileset_file regs.sv SYSTEM_VERILOG PATH rtl/core/regs/regs.sv
-add_fileset_file exclusive.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/exclusive.sv
 
 
 # 
diff --git a/perf_hw.tcl b/perf_hw.tcl
index d3941d9..47cca9e 100644
--- a/perf_hw.tcl
+++ b/perf_hw.tcl
@@ -40,8 +40,8 @@ set_fileset_property QUARTUS_SYNTH TOP_LEVEL perf_monitor
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
 add_fileset_file perf_monitor.sv SYSTEM_VERILOG PATH rtl/perf/perf_monitor.sv TOP_LEVEL_FILE
-add_fileset_file link.sv SYSTEM_VERILOG PATH rtl/perf/link.sv
-add_fileset_file snoop.sv SYSTEM_VERILOG PATH rtl/perf/snoop.sv
+add_fileset_file perf_link.sv SYSTEM_VERILOG PATH rtl/perf/perf_link.sv
+add_fileset_file perf_snoop.sv SYSTEM_VERILOG PATH rtl/perf/perf_snoop.sv
 
 
 # 
diff --git a/rtl/cache/mem.sv b/rtl/cache/cache_mem.sv
index a575d0d..a575d0d 100644
--- a/rtl/cache/mem.sv
+++ b/rtl/cache/cache_mem.sv
diff --git a/rtl/cache/monitor.sv b/rtl/cache/cache_monitor.sv
index 380019e..380019e 100644
--- a/rtl/cache/monitor.sv
+++ b/rtl/cache/cache_monitor.sv
diff --git a/rtl/cache/offsets.sv b/rtl/cache/cache_offsets.sv
index 7769394..7769394 100644
--- a/rtl/cache/offsets.sv
+++ b/rtl/cache/cache_offsets.sv
diff --git a/rtl/cache/ring.sv b/rtl/cache/cache_ring.sv
index d934fb7..d934fb7 100644
--- a/rtl/cache/ring.sv
+++ b/rtl/cache/cache_ring.sv
diff --git a/rtl/cache/routing.sv b/rtl/cache/cache_routing.sv
index a0c4347..a0c4347 100644
--- a/rtl/cache/routing.sv
+++ b/rtl/cache/cache_routing.sv
diff --git a/rtl/cache/sram.sv b/rtl/cache/cache_sram.sv
index d63cdad..d63cdad 100644
--- a/rtl/cache/sram.sv
+++ b/rtl/cache/cache_sram.sv
diff --git a/rtl/cache/token.sv b/rtl/cache/cache_token.sv
index cb3e59d..cb3e59d 100644
--- a/rtl/cache/token.sv
+++ b/rtl/cache/cache_token.sv
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index cfe202a..66493e2 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -1,4 +1,4 @@
-`include "core/mmu/format.sv"
+`include "core/mmu_format.sv"
 `include "core/uarch.sv"
 
 module arm810
diff --git a/rtl/core/alu/alu.sv b/rtl/core/core_alu.sv
index c0ccd32..6dafa65 100644
--- a/rtl/core/alu/alu.sv
+++ b/rtl/core/core_alu.sv
@@ -1,5 +1,5 @@
+`include "core/isa.sv"
 `include "core/uarch.sv"
-`include "core/decode/isa.sv"
 
 module core_alu
 #(parameter W=16)
diff --git a/rtl/core/alu/add.sv b/rtl/core/core_alu_add.sv
index a15a6b6..a15a6b6 100644
--- a/rtl/core/alu/add.sv
+++ b/rtl/core/core_alu_add.sv
diff --git a/rtl/core/alu/and.sv b/rtl/core/core_alu_and.sv
index d119f24..d119f24 100644
--- a/rtl/core/alu/and.sv
+++ b/rtl/core/core_alu_and.sv
diff --git a/rtl/core/alu/orr.sv b/rtl/core/core_alu_orr.sv
index 1ee87c2..1ee87c2 100644
--- a/rtl/core/alu/orr.sv
+++ b/rtl/core/core_alu_orr.sv
diff --git a/rtl/core/alu/xor.sv b/rtl/core/core_alu_xor.sv
index f55dfc2..f55dfc2 100644
--- a/rtl/core/alu/xor.sv
+++ b/rtl/core/core_alu_xor.sv
diff --git a/rtl/core/control/control.sv b/rtl/core/core_control.sv
index 27be940..27be940 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/core_control.sv
diff --git a/rtl/core/control/branch.sv b/rtl/core/core_control_branch.sv
index 0298b95..0298b95 100644
--- a/rtl/core/control/branch.sv
+++ b/rtl/core/core_control_branch.sv
diff --git a/rtl/core/control/coproc.sv b/rtl/core/core_control_coproc.sv
index 05ac655..05ac655 100644
--- a/rtl/core/control/coproc.sv
+++ b/rtl/core/core_control_coproc.sv
diff --git a/rtl/core/control/cycles.sv b/rtl/core/core_control_cycles.sv
index 772697d..772697d 100644
--- a/rtl/core/control/cycles.sv
+++ b/rtl/core/core_control_cycles.sv
diff --git a/rtl/core/control/data.sv b/rtl/core/core_control_data.sv
index 3174ee1..3174ee1 100644
--- a/rtl/core/control/data.sv
+++ b/rtl/core/core_control_data.sv
diff --git a/rtl/core/control/debug.sv b/rtl/core/core_control_debug.sv
index 35b1334..35b1334 100644
--- a/rtl/core/control/debug.sv
+++ b/rtl/core/core_control_debug.sv
diff --git a/rtl/core/control/exception.sv b/rtl/core/core_control_exception.sv
index 387e9c1..387e9c1 100644
--- a/rtl/core/control/exception.sv
+++ b/rtl/core/core_control_exception.sv
diff --git a/rtl/core/control/issue.sv b/rtl/core/core_control_issue.sv
index 5bd03e1..5bd03e1 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/core_control_issue.sv
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/core_control_ldst.sv
index aa5c957..aa5c957 100644
--- a/rtl/core/control/ldst/ldst.sv
+++ b/rtl/core/core_control_ldst.sv
diff --git a/rtl/core/control/ldst/pop.sv b/rtl/core/core_control_ldst_pop.sv
index 64dc04d..64dc04d 100644
--- a/rtl/core/control/ldst/pop.sv
+++ b/rtl/core/core_control_ldst_pop.sv
diff --git a/rtl/core/control/ldst/sizes.sv b/rtl/core/core_control_ldst_sizes.sv
index dff4662..dff4662 100644
--- a/rtl/core/control/ldst/sizes.sv
+++ b/rtl/core/core_control_ldst_sizes.sv
diff --git a/rtl/core/control/mul_fu.sv b/rtl/core/core_control_mul.sv
index 8352435..8352435 100644
--- a/rtl/core/control/mul_fu.sv
+++ b/rtl/core/core_control_mul.sv
diff --git a/rtl/core/control/status.sv b/rtl/core/core_control_psr.sv
index 6616bc9..6616bc9 100644
--- a/rtl/core/control/status.sv
+++ b/rtl/core/core_control_psr.sv
diff --git a/rtl/core/control/select.sv b/rtl/core/core_control_select.sv
index dc04282..dc04282 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/core_control_select.sv
diff --git a/rtl/core/control/stall.sv b/rtl/core/core_control_stall.sv
index 02a7552..02a7552 100644
--- a/rtl/core/control/stall.sv
+++ b/rtl/core/core_control_stall.sv
diff --git a/rtl/core/control/writeback.sv b/rtl/core/core_control_writeback.sv
index 027a7d7..027a7d7 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/core_control_writeback.sv
diff --git a/rtl/core/cp15/cp15.sv b/rtl/core/core_cp15.sv
index 5a482d4..09b899a 100644
--- a/rtl/core/cp15/cp15.sv
+++ b/rtl/core/core_cp15.sv
@@ -1,5 +1,5 @@
-`include "core/cp15/map.sv"
-`include "core/mmu/format.sv"
+`include "core/cp15_map.sv"
+`include "core/mmu_format.sv"
 `include "core/uarch.sv"
 
 module core_cp15
diff --git a/rtl/core/cp15/cache_ops.sv b/rtl/core/core_cp15_cache.sv
index cb6d4ad..cb6d4ad 100644
--- a/rtl/core/cp15/cache_ops.sv
+++ b/rtl/core/core_cp15_cache.sv
diff --git a/rtl/core/cp15/cache_lockdown.sv b/rtl/core/core_cp15_cache_lockdown.sv
index 65d4c0f..65d4c0f 100644
--- a/rtl/core/cp15/cache_lockdown.sv
+++ b/rtl/core/core_cp15_cache_lockdown.sv
diff --git a/rtl/core/cp15/cpuid.sv b/rtl/core/core_cp15_cpuid.sv
index c9cab59..6e23c7e 100644
--- a/rtl/core/cp15/cpuid.sv
+++ b/rtl/core/core_cp15_cpuid.sv
@@ -1,5 +1,5 @@
 `include "core/uarch.sv"
-`include "core/cp15/map.sv"
+`include "core/cp15_map.sv"
 
 module core_cp15_cpuid
 (
diff --git a/rtl/core/cp15/cyclecnt.sv b/rtl/core/core_cp15_cyclecnt.sv
index b079a1b..b079a1b 100644
--- a/rtl/core/cp15/cyclecnt.sv
+++ b/rtl/core/core_cp15_cyclecnt.sv
diff --git a/rtl/core/cp15/domain.sv b/rtl/core/core_cp15_domain.sv
index de37de4..de37de4 100644
--- a/rtl/core/cp15/domain.sv
+++ b/rtl/core/core_cp15_domain.sv
diff --git a/rtl/core/cp15/far.sv b/rtl/core/core_cp15_far.sv
index 36e76db..ca1dcf1 100644
--- a/rtl/core/cp15/far.sv
+++ b/rtl/core/core_cp15_far.sv
@@ -1,5 +1,5 @@
 `include "core/uarch.sv"
-`include "core/cp15/map.sv"
+`include "core/cp15_map.sv"
 
 module core_cp15_far
 (
diff --git a/rtl/core/cp15/fsr.sv b/rtl/core/core_cp15_fsr.sv
index 81b4992..b388d00 100644
--- a/rtl/core/cp15/fsr.sv
+++ b/rtl/core/core_cp15_fsr.sv
@@ -1,5 +1,5 @@
-`include "core/cp15/map.sv"
-`include "core/mmu/format.sv"
+`include "core/cp15_map.sv"
+`include "core/mmu_format.sv"
 `include "core/uarch.sv"
 
 module core_cp15_fsr
diff --git a/rtl/core/cp15/syscfg.sv b/rtl/core/core_cp15_syscfg.sv
index 5bd2530..cdd6014 100644
--- a/rtl/core/cp15/syscfg.sv
+++ b/rtl/core/core_cp15_syscfg.sv
@@ -1,5 +1,5 @@
 `include "core/uarch.sv"
-`include "core/cp15/map.sv"
+`include "core/cp15_map.sv"
 
 module core_cp15_syscfg
 (
diff --git a/rtl/core/cp15/tlb.sv b/rtl/core/core_cp15_tlb.sv
index 5cbd19d..5cbd19d 100644
--- a/rtl/core/cp15/tlb.sv
+++ b/rtl/core/core_cp15_tlb.sv
diff --git a/rtl/core/cp15/tlb_lockdown.sv b/rtl/core/core_cp15_tlb_lockdown.sv
index 1972c33..1972c33 100644
--- a/rtl/core/cp15/tlb_lockdown.sv
+++ b/rtl/core/core_cp15_tlb_lockdown.sv
diff --git a/rtl/core/cp15/ttbr.sv b/rtl/core/core_cp15_ttbr.sv
index b462955..3b1a76a 100644
--- a/rtl/core/cp15/ttbr.sv
+++ b/rtl/core/core_cp15_ttbr.sv
@@ -1,5 +1,5 @@
-`include "core/cp15/map.sv"
-`include "core/mmu/format.sv"
+`include "core/cp15_map.sv"
+`include "core/mmu_format.sv"
 `include "core/uarch.sv"
 
 module core_cp15_ttbr
diff --git a/rtl/core/decode/decode.sv b/rtl/core/core_decode.sv
index 219f975..b43c239 100644
--- a/rtl/core/decode/decode.sv
+++ b/rtl/core/core_decode.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode
diff --git a/rtl/core/decode/branch_dec.sv b/rtl/core/core_decode_branch.sv
index 1dbc1ad..9916374 100644
--- a/rtl/core/decode/branch_dec.sv
+++ b/rtl/core/core_decode_branch.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_branch
diff --git a/rtl/core/decode/coproc_dec.sv b/rtl/core/core_decode_coproc.sv
index 153cadf..c9a68c7 100644
--- a/rtl/core/decode/coproc_dec.sv
+++ b/rtl/core/core_decode_coproc.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_coproc
diff --git a/rtl/core/decode/data_dec.sv b/rtl/core/core_decode_data.sv
index f744972..a4e993e 100644
--- a/rtl/core/decode/data_dec.sv
+++ b/rtl/core/core_decode_data.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_data
diff --git a/rtl/core/decode/ldst/addr.sv b/rtl/core/core_decode_ldst_addr.sv
index 345f0ea..345f0ea 100644
--- a/rtl/core/decode/ldst/addr.sv
+++ b/rtl/core/core_decode_ldst_addr.sv
diff --git a/rtl/core/decode/ldst/exclusive.sv b/rtl/core/core_decode_ldst_exclusive.sv
index 7942a04..f45cbfa 100644
--- a/rtl/core/decode/ldst/exclusive.sv
+++ b/rtl/core/core_decode_ldst_exclusive.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_ldst_exclusive
diff --git a/rtl/core/decode/ldst/misc.sv b/rtl/core/core_decode_ldst_misc.sv
index 72d648c..bedbdf4 100644
--- a/rtl/core/decode/ldst/misc.sv
+++ b/rtl/core/core_decode_ldst_misc.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_ldst_misc
diff --git a/rtl/core/decode/ldst/multiple.sv b/rtl/core/core_decode_ldst_multiple.sv
index c822ab0..234bd56 100644
--- a/rtl/core/decode/ldst/multiple.sv
+++ b/rtl/core/core_decode_ldst_multiple.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_ldst_multiple
diff --git a/rtl/core/decode/ldst/single.sv b/rtl/core/core_decode_ldst_single.sv
index af096a7..0f47a30 100644
--- a/rtl/core/decode/ldst/single.sv
+++ b/rtl/core/core_decode_ldst_single.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_ldst_single
diff --git a/rtl/core/decode/mrs.sv b/rtl/core/core_decode_mrs.sv
index 05018cd..8e4b19b 100644
--- a/rtl/core/decode/mrs.sv
+++ b/rtl/core/core_decode_mrs.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_mrs
diff --git a/rtl/core/decode/msr.sv b/rtl/core/core_decode_msr.sv
index c3f0e3d..3f10255 100644
--- a/rtl/core/decode/msr.sv
+++ b/rtl/core/core_decode_msr.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_msr
diff --git a/rtl/core/decode/mul_dec.sv b/rtl/core/core_decode_mul.sv
index 114b65b..88cc422 100644
--- a/rtl/core/decode/mul_dec.sv
+++ b/rtl/core/core_decode_mul.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_mul
diff --git a/rtl/core/decode/mux.sv b/rtl/core/core_decode_mux.sv
index 6f0451a..f90ee49 100644
--- a/rtl/core/decode/mux.sv
+++ b/rtl/core/core_decode_mux.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_mux
diff --git a/rtl/core/decode/snd.sv b/rtl/core/core_decode_snd.sv
index 264982e..3ee8722 100644
--- a/rtl/core/decode/snd.sv
+++ b/rtl/core/core_decode_snd.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_snd
diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/core_fetch.sv
index 279d2c2..279d2c2 100644
--- a/rtl/core/fetch/fetch.sv
+++ b/rtl/core/core_fetch.sv
diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/core_mmu.sv
index 22dfc3b..3060d69 100644
--- a/rtl/core/mmu/mmu.sv
+++ b/rtl/core/core_mmu.sv
@@ -1,4 +1,4 @@
-`include "core/mmu/format.sv"
+`include "core/mmu_format.sv"
 `include "core/uarch.sv"
 
 module core_mmu
diff --git a/rtl/core/mmu/arbiter.sv b/rtl/core/core_mmu_arbiter.sv
index b0da7c8..b0da7c8 100644
--- a/rtl/core/mmu/arbiter.sv
+++ b/rtl/core/core_mmu_arbiter.sv
diff --git a/rtl/core/mmu/fault.sv b/rtl/core/core_mmu_fault.sv
index b33cec2..ec80753 100644
--- a/rtl/core/mmu/fault.sv
+++ b/rtl/core/core_mmu_fault.sv
@@ -1,4 +1,4 @@
-`include "core/mmu/format.sv"
+`include "core/mmu_format.sv"
 `include "core/uarch.sv"
 
 module core_mmu_fault
diff --git a/rtl/core/mmu/pagewalk.sv b/rtl/core/core_mmu_pagewalk.sv
index 70c932c..bdf1989 100644
--- a/rtl/core/mmu/pagewalk.sv
+++ b/rtl/core/core_mmu_pagewalk.sv
@@ -1,4 +1,4 @@
-`include "core/mmu/format.sv"
+`include "core/mmu_format.sv"
 `include "core/uarch.sv"
 
 module core_mmu_pagewalk
diff --git a/rtl/core/mul.sv b/rtl/core/core_mul.sv
index 19bbb9a..19bbb9a 100644
--- a/rtl/core/mul.sv
+++ b/rtl/core/core_mul.sv
diff --git a/rtl/core/porch/porch.sv b/rtl/core/core_porch.sv
index 060ab91..060ab91 100644
--- a/rtl/core/porch/porch.sv
+++ b/rtl/core/core_porch.sv
diff --git a/rtl/core/porch/conds.sv b/rtl/core/core_porch_conds.sv
index b8db1e7..3d00e12 100644
--- a/rtl/core/porch/conds.sv
+++ b/rtl/core/core_porch_conds.sv
@@ -1,4 +1,4 @@
-`include "core/decode/isa.sv"
+`include "core/isa.sv"
 `include "core/uarch.sv"
 
 module core_porch_conds
diff --git a/rtl/core/fetch/prefetch.sv b/rtl/core/core_prefetch.sv
index 719ad95..719ad95 100644
--- a/rtl/core/fetch/prefetch.sv
+++ b/rtl/core/core_prefetch.sv
diff --git a/rtl/core/psr.sv b/rtl/core/core_psr.sv
index 7bbffe6..7bbffe6 100644
--- a/rtl/core/psr.sv
+++ b/rtl/core/core_psr.sv
diff --git a/rtl/core/regs/file.sv b/rtl/core/core_reg_file.sv
index 2ba95e8..2ba95e8 100644
--- a/rtl/core/regs/file.sv
+++ b/rtl/core/core_reg_file.sv
diff --git a/rtl/core/regs/reg_map.sv b/rtl/core/core_reg_map.sv
index 11085d4..11085d4 100644
--- a/rtl/core/regs/reg_map.sv
+++ b/rtl/core/core_reg_map.sv
diff --git a/rtl/core/regs/regs.sv b/rtl/core/core_regs.sv
index f9cecad..f9cecad 100644
--- a/rtl/core/regs/regs.sv
+++ b/rtl/core/core_regs.sv
diff --git a/rtl/core/shifter.sv b/rtl/core/core_shifter.sv
index 96b8866..96b8866 100644
--- a/rtl/core/shifter.sv
+++ b/rtl/core/core_shifter.sv
diff --git a/rtl/core/cp15/map.sv b/rtl/core/cp15_map.sv
index 438a5bf..438a5bf 100644
--- a/rtl/core/cp15/map.sv
+++ b/rtl/core/cp15_map.sv
diff --git a/rtl/core/decode/isa.sv b/rtl/core/isa.sv
index 6784eca..6784eca 100644
--- a/rtl/core/decode/isa.sv
+++ b/rtl/core/isa.sv
diff --git a/rtl/core/mmu/format.sv b/rtl/core/mmu_format.sv
index 3029b83..3029b83 100644
--- a/rtl/core/mmu/format.sv
+++ b/rtl/core/mmu_format.sv
diff --git a/rtl/perf/link.sv b/rtl/perf/perf_link.sv
index 323af45..323af45 100644
--- a/rtl/perf/link.sv
+++ b/rtl/perf/perf_link.sv
diff --git a/rtl/perf/snoop.sv b/rtl/perf/perf_snoop.sv
index e98153e..e98153e 100644
--- a/rtl/perf/snoop.sv
+++ b/rtl/perf/perf_snoop.sv
diff --git a/rtl/smp/pe.sv b/rtl/smp/smp_pe.sv
index 5c675ee..5c675ee 100644
--- a/rtl/smp/pe.sv
+++ b/rtl/smp/smp_pe.sv
diff --git a/smp_hw.tcl b/smp_hw.tcl
index a853287..6093f87 100644
--- a/smp_hw.tcl
+++ b/smp_hw.tcl
@@ -40,7 +40,7 @@ set_fileset_property QUARTUS_SYNTH TOP_LEVEL smp_ctrl
 set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
 set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
 add_fileset_file smp_ctrl.sv SYSTEM_VERILOG PATH rtl/smp/smp_ctrl.sv TOP_LEVEL_FILE
-add_fileset_file pe.sv SYSTEM_VERILOG PATH rtl/smp/pe.sv
+add_fileset_file smp_pe.sv SYSTEM_VERILOG PATH rtl/smp/smp_pe.sv
 
 
 #