summaryrefslogtreecommitdiff
path: root/rtl/core/core_control_branch.sv
diff options
context:
space:
mode:
Diffstat (limited to 'rtl/core/core_control_branch.sv')
-rw-r--r--rtl/core/core_control_branch.sv30
1 files changed, 30 insertions, 0 deletions
diff --git a/rtl/core/core_control_branch.sv b/rtl/core/core_control_branch.sv
new file mode 100644
index 0000000..0298b95
--- /dev/null
+++ b/rtl/core/core_control_branch.sv
@@ -0,0 +1,30 @@
+`include "core/uarch.sv"
+
+module core_control_branch
+(
+ input logic clk,
+ rst_n,
+
+ input insn_decode dec,
+
+ input ctrl_cycle next_cycle,
+ input logic issue,
+ input ptr next_pc_visible,
+
+ output logic branch,
+ output ptr branch_target
+);
+
+ always_ff @(posedge clk or negedge rst_n)
+ if(!rst_n) begin
+ branch <= 1;
+ branch_target <= {$bits(branch_target){1'b0}};
+ end else begin
+ branch <= 0;
+ if(next_cycle.issue && issue) begin
+ branch <= dec.ctrl.branch;
+ branch_target <= next_pc_visible + dec.branch.offset;
+ end
+ end
+
+endmodule