diff options
| author | Alejandro Soto <alejandro@34project.org> | 2024-01-21 06:23:46 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-02-20 11:11:17 -0600 |
| commit | f3b18ead59ae02f95dabbf0a1dea40873a816975 (patch) | |
| tree | 8979e50f2a37f66a4cd27e937b480efe60d72cf7 /rtl/core/core_control_branch.sv | |
| parent | a8bc5a353ea997f73209b39377ee15a73e471237 (diff) | |
rtl: refactor filenames and directory hierarchy
Diffstat (limited to 'rtl/core/core_control_branch.sv')
| -rw-r--r-- | rtl/core/core_control_branch.sv | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/rtl/core/core_control_branch.sv b/rtl/core/core_control_branch.sv new file mode 100644 index 0000000..0298b95 --- /dev/null +++ b/rtl/core/core_control_branch.sv @@ -0,0 +1,30 @@ +`include "core/uarch.sv" + +module core_control_branch +( + input logic clk, + rst_n, + + input insn_decode dec, + + input ctrl_cycle next_cycle, + input logic issue, + input ptr next_pc_visible, + + output logic branch, + output ptr branch_target +); + + always_ff @(posedge clk or negedge rst_n) + if(!rst_n) begin + branch <= 1; + branch_target <= {$bits(branch_target){1'b0}}; + end else begin + branch <= 0; + if(next_cycle.issue && issue) begin + branch <= dec.ctrl.branch; + branch_target <= next_pc_visible + dec.branch.offset; + end + end + +endmodule |
