Add cp15 cyclecnt clock source

1 files changed, 23 insertions, 0 deletions

diff --git a/rtl/core/cp15/cyclecnt.sv b/rtl/core/cp15/cyclecnt.sv
new file mode 100644
index 0000000..b079a1b
--- /dev/null
+++ b/rtl/core/cp15/cyclecnt.sv
@@ -0,0 +1,23 @@
+`include "core/uarch.sv"
+
+module core_cp15_cyclecnt
+(
+	input  logic     clk,
+	                 rst_n,
+
+	input  logic     halt,
+
+	output word      read
+);
+
+	word cyclecnt;
+
+	assign read = cyclecnt;
+
+	always @(posedge clk or negedge rst_n)
+		if(!rst_n)
+			cyclecnt <= 0;
+		else if(!halt)
+			cyclecnt <= cyclecnt + 1;
+
+endmodule