From 1f94f0eb7e214bff29468bf9c39cb99520e290f2 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 13 Dec 2022 14:59:33 -0600 Subject: Add cp15 cyclecnt clock source --- rtl/core/cp15/cyclecnt.sv | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 rtl/core/cp15/cyclecnt.sv (limited to 'rtl/core/cp15/cyclecnt.sv') diff --git a/rtl/core/cp15/cyclecnt.sv b/rtl/core/cp15/cyclecnt.sv new file mode 100644 index 0000000..b079a1b --- /dev/null +++ b/rtl/core/cp15/cyclecnt.sv @@ -0,0 +1,23 @@ +`include "core/uarch.sv" + +module core_cp15_cyclecnt +( + input logic clk, + rst_n, + + input logic halt, + + output word read +); + + word cyclecnt; + + assign read = cyclecnt; + + always @(posedge clk or negedge rst_n) + if(!rst_n) + cyclecnt <= 0; + else if(!halt) + cyclecnt <= cyclecnt + 1; + +endmodule -- cgit v1.2.3