index
:
conspiracion
master
Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
tb
/
sim
(
follow
)
Age
Commit message (
Collapse
)
Author
2024-02-20
tb/sim: update constant in hazards test
Alejandro Soto
2023-10-05
tb/sim/sdram: lower max cycles
Alejandro Soto
2023-10-04
app, doc, image_processing, tb/sim/descifrador: remove;5D
Alejandro Soto
2023-10-03
tb/sim/strex: test monitor after exception
Alejandro Soto
2023-10-03
tb/sim: add test: strex
Alejandro Soto
2023-10-02
tb/sim: add test: smp_boot
Alejandro Soto
2023-09-25
rtl/cache: fix writeback corruption
Alejandro Soto
2023-09-25
tb: implement cache ring
Alejandro Soto
2022-12-18
Implement privileged ldm/stm of user registers
Alejandro Soto
2022-12-18
Fix datapath of shifter carry-out during adc/sbc/rsc
Alejandro Soto
2022-12-16
Implement swi (system call)
Alejandro Soto
2022-12-16
Fix register corruption when interrupting a load-store
Alejandro Soto
2022-12-16
Implement interrupt emulation
Alejandro Soto
2022-12-16
Implement fast video
Alejandro Soto
2022-12-16
Implement prefetch aborts
Alejandro Soto
2022-12-16
Implement MMU access checks
Alejandro Soto
2022-12-16
Implement data aborts
Alejandro Soto
2022-12-16
Implement hardware virtual memory
Alejandro Soto
2022-12-09
Implement CP15 ID register
Alejandro Soto
2022-12-09
Implement cp15 control
Alejandro Soto
2022-12-08
Fix decoding of msr with immediate operand
Alejandro Soto
2022-12-07
Fix register-indirect shifts
Alejandro Soto
2022-12-06
Implement gdbstub
Alejandro Soto
2022-11-19
Implement JTAG-UART input
Alejandro Soto
2022-11-17
Finish simulation
Alejandro Soto
2022-11-17
Fix sim
Alejandro Soto
2022-11-17
Implement sim test: descifrador
Alejandro Soto
2022-11-17
Bug fixes
JulianCamacho
2022-11-16
Implement bx lr
Alejandro Soto
2022-11-16
Implement privilege escalation
Alejandro Soto
2022-11-16
Implement psr read/write logic
Alejandro Soto
2022-11-16
Add sim test: subword
Alejandro Soto
2022-11-14
Implement VGA simulation
Alejandro Soto
2022-11-10
Implement support for predictable x-values in sim
Alejandro Soto
2022-11-09
Improve sdram sim test
Alejandro Soto
2022-11-09
Implement initial state randomization in sim
Alejandro Soto
2022-11-09
Fix bus protocol errors in bus master
Alejandro Soto
2022-11-08
Fix handling of multi-cycle Avalon waitrequest states in bus master
Alejandro Soto
2022-11-08
Add sim: sdram
Alejandro Soto
2022-11-07
Add test sim: modeswitch
Alejandro Soto
2022-11-07
Improve mult sim
Alejandro Soto
2022-10-31
Show simulator output in sim testbenches
Alejandro Soto
2022-10-25
Implement explicit sim state dump
Alejandro Soto
2022-10-25
Add sim test: tarea2
Alejandro Soto
2022-10-23
Add sim test: shifts
Alejandro Soto
2022-10-23
Add sim test: stack
Alejandro Soto
2022-10-18
Add sim test: control_flow
Alejandro Soto
2022-10-18
Add sim test: mult
Alejandro Soto
2022-10-18
Print simulator command line on test failure
Alejandro Soto
2022-10-18
Support skipping tests
Alejandro Soto
[next]