diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-12-14 22:24:58 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-16 16:29:10 -0600 |
| commit | ef151fffb14eac19a19121dfb4c1e015e7470038 (patch) | |
| tree | d3fe7d47e26bbf83cf2d38986e5f823d4e5dbb98 /tb/sim | |
| parent | d2be560fa668cefcc5eff6b88180f12fec0c326e (diff) | |
Fix register corruption when interrupting a load-store
Diffstat (limited to 'tb/sim')
| -rw-r--r-- | tb/sim/irq.S | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tb/sim/irq.S b/tb/sim/irq.S index 35ce2c9..2ed4621 100644 --- a/tb/sim/irq.S +++ b/tb/sim/irq.S @@ -29,6 +29,25 @@ reset: str r1, [r2, #4] .wfi: + # Una secuencia de load-stores intensos como esta se encuentra en el + # código de calibración de delay loop del kernel. Antes del commit + # con título 'Fix register corruption when interrupting a load-store', + # una IRQ justo aquí provcaba que el core entrara en un estado indefinido. + # En el caso de Linux, eso resultaba en kernel panics indepurables. + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] + ldr r10, [r2] tst r0, r0 beq .wfi |