| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-11-09 | Add reset signal to bus master | Alejandro Soto |
| 2022-11-03 | Add toplevel wires for VGA DAC | Alejandro Soto |
| 2022-11-02 | Add bus master forward signals: irq, cpu_clk | Alejandro Soto |
| 2022-11-02 | Add new toplevel signals | Alejandro Soto |
| 2022-09-18 | Rename data_rw to data_wr in bus master | Alejandro Soto |
| 2022-09-18 | Fix public_flat_rw signals | Alejandro Soto |
| 2022-09-18 | Update testbench | Alejandro Soto |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |