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AgeCommit message (Expand)Author
2023-10-05Makefile, tb: add support for cocotbAlejandro Soto
2023-10-04rtl/cache: implement debug interfaceAlejandro Soto
2023-10-02tb: implement verilated slavesAlejandro Soto
2023-10-02rtl: implement exclusive monitor datapathAlejandro Soto
2023-10-01tb: implement quad-core SMPAlejandro Soto
2023-09-30platform: implement SMP controllerAlejandro Soto
2023-09-26rtl/mp: fix designAlejandro Soto
2023-09-25rtl/core, tb: replace bus_master with a new top-level moduleAlejandro Soto
2023-09-25tb: implement cache ringAlejandro Soto
2022-11-17Bug fixesJulianCamacho
2022-11-15Implemente byte-enable signal in storesAlejandro Soto
2022-11-15Replace vga_controller with streaming Altera IPAlejandro Soto
2022-11-14Implement VGA simulationAlejandro Soto
2022-11-13Route cpu_rst_n signal through bus masterAlejandro Soto
2022-11-13Hardwire PLL reset to groundAlejandro Soto
2022-11-09Implement initial state randomization in simAlejandro Soto
2022-11-09Implement resetAlejandro Soto
2022-11-09Add reset signal to bus masterAlejandro Soto
2022-11-03Add toplevel wires for VGA DACAlejandro Soto
2022-11-02Add bus master forward signals: irq, cpu_clkAlejandro Soto
2022-11-02Add new toplevel signalsAlejandro Soto
2022-09-18Rename data_rw to data_wr in bus masterAlejandro Soto
2022-09-18Fix public_flat_rw signalsAlejandro Soto
2022-09-18Update testbenchAlejandro Soto