index
:
conspiracion
master
Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
rtl
/
core
(
follow
)
Age
Commit message (
Expand
)
Author
2022-12-16
Show main cp15 registers in register dumps
Alejandro Soto
2022-12-16
Implement prefetch aborts
Alejandro Soto
2022-12-16
Implement register writes from gdb
Alejandro Soto
2022-12-16
Implement MMU access checks
Alejandro Soto
2022-12-16
Implement data aborts
Alejandro Soto
2022-12-16
Implement hardware virtual memory
Alejandro Soto
2022-12-10
Expose cp15 signals to core toplevel
Alejandro Soto
2022-12-10
Implement rest of cp15 registers
Alejandro Soto
2022-12-09
Implement CP15 ID register
Alejandro Soto
2022-12-09
Implement cp15 control
Alejandro Soto
2022-12-08
Fix decoding of msr with immediate operand
Alejandro Soto
2022-12-07
Fix register-indirect shifts
Alejandro Soto
2022-12-07
Implement single-stepping
Alejandro Soto
2022-12-06
Implement breakpoints
Alejandro Soto
2022-11-16
Fix carry flag bug
Alejandro Soto
2022-11-16
Implement bx lr
Alejandro Soto
2022-11-16
Implement privilege escalation
Alejandro Soto
2022-11-16
Implement psr read/write logic
Alejandro Soto
2022-11-16
Simplify flags datapath
Alejandro Soto
2022-11-16
Finish decode of psr operations
Alejandro Soto
2022-11-16
Fix final_writeback condition bug
Alejandro Soto
2022-11-16
Fix decoding of LDST_MISC group
Alejandro Soto
2022-11-15
Implemente byte-enable signal in stores
Alejandro Soto
2022-11-15
Fix false undefined exception
Alejandro Soto
2022-11-15
Fix shr carry bug
Alejandro Soto
2022-11-15
Implement sub-word memory accesses
Alejandro Soto
2022-11-15
Rewrite duplicate ldst logic as signal ldst_next
Alejandro Soto
2022-11-15
Add untested warning to mul.sv
Alejandro Soto
2022-11-15
Mpve combinational logic out of arm810.sv
Alejandro Soto
2022-11-15
Rename existing MMU components to MMU arbiter
Alejandro Soto
2022-11-13
Fix big Quartus state transition bug
Alejandro Soto
2022-11-13
Convert core state machines to Quartus-inferring RTL
Alejandro Soto
2022-11-13
Implement CPU halt
Alejandro Soto
2022-11-13
Simplify stall conditions to reflect uarch changes
Alejandro Soto
2022-11-10
Fix fetch discard glitches on flush
Alejandro Soto
2022-11-10
Fix reset glitches
Alejandro Soto
2022-11-10
Fix flush-stall relationship in porch
Alejandro Soto
2022-11-09
Implement reset
Alejandro Soto
2022-11-08
Improve ALU performance
Alejandro Soto
2022-11-08
Register decode output in a new porch stage
Alejandro Soto
2022-11-08
Rename datapath_decode as ctrl_decode
Alejandro Soto
2022-11-08
Refactor decode signals into unified insn_decode struct
Alejandro Soto
2022-11-07
Fix flags hazard in ADC, SBC, RSC
Alejandro Soto
2022-11-07
Remove false dependencies on control.issue (long combinational)
Alejandro Soto
2022-11-07
Fix long combinational path between regs and fetch
Alejandro Soto
2022-11-07
Rework regfile in order to remove negedge trigger
Alejandro Soto
2022-11-07
Quartus has not support for unique0
Alejandro Soto
2022-11-07
Implement multiplication control
Alejandro Soto
2022-11-07
Split decode mux logic out of decode.sv
Alejandro Soto
2022-11-06
Add PSR control signal set
Alejandro Soto
[next]