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authorAlejandro Soto <alejandro@34project.org>2022-11-16 19:12:28 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-16 23:32:25 -0600
commite33c30734b475879318b4f5c178a2f3bf2090bbb (patch)
tree611a941f619f9a35fa4e0f39d3b5bfd23b5cfe2c /rtl/core
parent739a690947165c4c319d2dbd76d4368bf4b59b5a (diff)
Implement bx lr
Diffstat (limited to 'rtl/core')
-rw-r--r--rtl/core/decode/isa.sv3
-rw-r--r--rtl/core/decode/mux.sv14
2 files changed, 17 insertions, 0 deletions
diff --git a/rtl/core/decode/isa.sv b/rtl/core/decode/isa.sv
index 1273a8b..7c27f49 100644
--- a/rtl/core/decode/isa.sv
+++ b/rtl/core/decode/isa.sv
@@ -48,6 +48,9 @@
`define INSN_B 28'b101_0_????????????????????????
`define INSN_BL 28'b101_1_????????????????????????
+// Esto no es parte de ARMv4, pero U-boot tiene algunos `bx lr` hard-coded
+`define INSN_BXLR 28'h12fff1e
+
`define GROUP_B 28'b101_?_????????????????????????
`define FIELD_B_L [24]
diff --git a/rtl/core/decode/mux.sv b/rtl/core/decode/mux.sv
index 51fe14b..3f613a4 100644
--- a/rtl/core/decode/mux.sv
+++ b/rtl/core/decode/mux.sv
@@ -216,6 +216,20 @@ module core_decode_mux
/*`GROUP_SWP: ;
`INSN_SWI: ;*/
+ /* No es parte de ARMv4 pero U-Boot lo necesita. esto se
+ * decodifica igual que `mov pc, lr` ya que no tenemos Thumb.
+ */
+ `INSN_BXLR: begin
+ dec_data.op = `ALU_MOV;
+ dec_data.rd = `R15;
+ dec_data.uses_rn = 0;
+
+ dec_snd.r = `R14;
+ dec_snd.is_imm = 0;
+
+ writeback = 1;
+ end
+
default:
undefined = 1;
endcase