| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-10-16 | Move isa.sv to core/decode | Alejandro Soto |
| 2022-10-09 | Implement most memory transactions | Alejandro Soto |
| 2022-10-08 | Implement LDR/STR decode | Alejandro Soto |
| 2022-10-02 | Split decoding of flexible second operand out of data instructions | Alejandro Soto |
| 2022-09-25 | Implement shifter decoding | Alejandro Soto |
| 2022-09-25 | Refactor CPSR and uarch.sv | Alejandro Soto |
| 2022-09-25 | Implement ALU | Alejandro Soto |
| 2022-09-25 | Implement register file | Alejandro Soto |
| 2022-09-24 | Implement decode of ALU instructions | Alejandro Soto |
| 2022-09-24 | Add instruction encodings | Alejandro Soto |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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