summaryrefslogtreecommitdiff
path: root/rtl/core/cycles.sv (follow)
AgeCommit message (Expand)Author
2022-10-15Fix flags and writeback hazardsAlejandro Soto
2022-10-15Fix branch target calculationAlejandro Soto
2022-10-09Implement most memory transactionsAlejandro Soto
2022-10-08Implement LDR/STR decodeAlejandro Soto
2022-10-08Rename EXECUTE cycle as ISSUEAlejandro Soto
2022-10-03Fix pipeline hazardsAlejandro Soto
2022-10-02Split decoding of flexible second operand out of data instructionsAlejandro Soto
2022-10-02Major shifter-ALU redesignAlejandro Soto
2022-09-27Switch from operand forwarding to next insn stalls (improves Fmax)Alejandro Soto
2022-09-26Fix writeback timingAlejandro Soto
2022-09-26Implement ALU shifterAlejandro Soto
2022-09-25Define ALU control signal setAlejandro Soto
2022-09-25Implement shifter decodingAlejandro Soto
2022-09-25Shorten decode_* nets to dec_*Alejandro Soto
2022-09-25Implement flag updatesAlejandro Soto
2022-09-25Refactor CPSR and uarch.svAlejandro Soto
2022-09-25Fix Quartus issuesAlejandro Soto
2022-09-25Implement PSR flag handlingAlejandro Soto
2022-09-25Implement initial cycle control logicAlejandro Soto
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 17:08:20 +0000