diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-10-08 15:34:46 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-08 15:34:46 -0600 |
| commit | dab6e68a8396475af5acbf53397f93c6b52e2e71 (patch) | |
| tree | 7ec0ee02735a730f633190acadaca23bbd574234 /rtl/core/cycles.sv | |
| parent | a0a12ef0c1bd6882d902a9d5938e7220e543b378 (diff) | |
Implement LDR/STR decode
Diffstat (limited to 'rtl/core/cycles.sv')
| -rw-r--r-- | rtl/core/cycles.sv | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv index ccf2d28..ddaf237 100644 --- a/rtl/core/cycles.sv +++ b/rtl/core/cycles.sv @@ -46,7 +46,7 @@ module core_cycles data_snd_is_imm, data_snd_shift_by_reg, trivial_shift; logic[5:0] data_shift_imm; - logic[7:0] data_imm; + logic[11:0] data_imm; word saved_base; reg_num r_shift, final_rd; ptr pc; @@ -87,7 +87,7 @@ module core_cycles unique case(cycle) ISSUE: if(data_snd_is_imm) - alu_b = {{24{1'b0}}, data_imm}; + alu_b = {{20{1'b0}}, data_imm}; else alu_b = rd_value_b; |