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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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rtl
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core
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control
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writeback.sv
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Author
2022-12-09
Implement cp15 control
Alejandro Soto
2022-11-16
Implement psr read/write logic
Alejandro Soto
2022-11-16
Simplify flags datapath
Alejandro Soto
2022-11-16
Fix final_writeback condition bug
Alejandro Soto
2022-11-15
Implement sub-word memory accesses
Alejandro Soto
2022-11-15
Rewrite duplicate ldst logic as signal ldst_next
Alejandro Soto
2022-11-13
Convert core state machines to Quartus-inferring RTL
Alejandro Soto
2022-11-10
Fix reset glitches
Alejandro Soto
2022-11-09
Implement reset
Alejandro Soto
2022-11-08
Refactor decode signals into unified insn_decode struct
Alejandro Soto
2022-11-07
Remove false dependencies on control.issue (long combinational)
Alejandro Soto
2022-11-07
Rework regfile in order to remove negedge trigger
Alejandro Soto
2022-11-07
Quartus has not support for unique0
Alejandro Soto
2022-11-07
Implement multiplication control
Alejandro Soto
2022-11-06
Add PSR control signal set
Alejandro Soto
2022-11-06
Clean-up control.sv
Alejandro Soto
2022-11-06
Move flag update logic to writeback.sv
Alejandro Soto
2022-11-06
Multiplex writeback control signals
Alejandro Soto