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authorAlejandro Soto <alejandro@34project.org>2022-11-06 15:12:26 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-06 15:12:26 -0600
commit5c73dd29b6629a37539ccb638a62d0a376f15bcb (patch)
treeb4351254828ab34b758e94f27aad5cd60f3d3f3f /rtl/core/control/writeback.sv
parentf4529ea2a6511f668fadbbc308439bcff6c9c53b (diff)
Move flag update logic to writeback.sv
Diffstat (limited to 'rtl/core/control/writeback.sv')
-rw-r--r--rtl/core/control/writeback.sv26
1 files changed, 25 insertions, 1 deletions
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index 2ba0845..021d494 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -24,6 +24,8 @@ module core_control_writeback
final_rd,
output logic writeback,
final_writeback,
+ update_flags,
+ final_update_flags,
output word wr_value
);
@@ -85,6 +87,23 @@ module core_control_writeback
default: wr_value <= q_alu;
endcase
+ update_flags <= 0;
+ unique0 case(next_cycle)
+ ISSUE:
+ update_flags <= final_update_flags;
+
+ EXCEPTION:
+ final_update_flags <= 0;
+ endcase
+
+ unique0 case(next_cycle)
+ ISSUE:
+ final_update_flags <= issue && dec.update_flags;
+
+ EXCEPTION:
+ final_update_flags <= 0;
+ endcase
+
unique0 case(next_cycle)
TRANSFER:
if(mem_ready)
@@ -101,9 +120,14 @@ module core_control_writeback
initial begin
rd = 0;
final_rd = 0;
- wr_value = 0;
+
writeback = 0;
final_writeback = 0;
+
+ update_flags = 0;
+ final_update_flags = 0;
+
+ wr_value = 0;
end
endmodule