| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-10-02 | Make the fetch stage use the bus arbiter | Alejandro Soto | |
| 2022-10-02 | Major shifter-ALU redesign | Alejandro Soto | |
| The shifter unit now works in parallel with the ALU and is no longer part of it. Instructions that use the shifter as input to the ALU will now take an additional cycle, unless the control unit can detect a "trivial shift" situation where the shifter's output will be the same as its input. This change improves Fmax substantially. | |||
| 2022-09-27 | Switch from operand forwarding to next insn stalls (improves Fmax) | Alejandro Soto | |
| 2022-09-27 | Implement branching in fetch stage | Alejandro Soto | |
| 2022-09-26 | Implement ALU shifter | Alejandro Soto | |
| 2022-09-25 | Define ALU control signal set | Alejandro Soto | |
| 2022-09-25 | Implement shifter decoding | Alejandro Soto | |
| 2022-09-25 | Shorten decode_* nets to dec_* | Alejandro Soto | |
| 2022-09-25 | Implement flag updates | Alejandro Soto | |
| 2022-09-25 | Refactor CPSR and uarch.sv | Alejandro Soto | |
| 2022-09-25 | Implement PSR flag handling | Alejandro Soto | |
| 2022-09-25 | Implement initial cycle control logic | Alejandro Soto | |
| 2022-09-24 | Implement initial decoder | Alejandro Soto | |
| 2022-09-23 | Implement core stub | Alejandro Soto | |
| It only has the fetch stage for now | |||
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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