| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-10-02 | Make the fetch stage use the bus arbiter | Alejandro Soto |
| 2022-10-02 | Major shifter-ALU redesign | Alejandro Soto |
| 2022-09-25 | Fix Quartus issues | Alejandro Soto |
| 2022-09-23 | Add toplevel module for core tests | Alejandro Soto |
| 2022-09-19 | DDR3 is working | Alejandro Soto |
| 2022-09-18 | Rename data_rw to data_wr in bus master | Alejandro Soto |
| 2022-09-17 | Update project structure to match Verilator Makefile | Alejandro Soto |
| 2022-09-04 | Add SDRAM test | Alejandro Soto |
| 2022-09-02 | Fix output buffer atom errors | Alejandro Soto |
| 2022-09-02 | Add hps_0 platform design | Alejandro Soto |
| 2022-09-01 | Initial commit | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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