diff options
Diffstat (limited to 'target/w3d_de1soc')
| -rw-r--r-- | target/w3d_de1soc/.gitignore | 1 | ||||
| -rw-r--r-- | target/w3d_de1soc/intc.sv | 30 | ||||
| -rw-r--r-- | target/w3d_de1soc/intc_hw.tcl | 168 | ||||
| -rw-r--r-- | target/w3d_de1soc/mod.mk | 14 | ||||
| -rw-r--r-- | target/w3d_de1soc/pins.tcl | 185 | ||||
| -rw-r--r-- | target/w3d_de1soc/platform.qsys | 1600 | ||||
| -rw-r--r-- | target/w3d_de1soc/timing.sdc | 3 | ||||
| -rw-r--r-- | target/w3d_de1soc/w3d_de1soc.sv | 429 |
8 files changed, 2430 insertions, 0 deletions
diff --git a/target/w3d_de1soc/.gitignore b/target/w3d_de1soc/.gitignore new file mode 100644 index 0000000..6ba7f8f --- /dev/null +++ b/target/w3d_de1soc/.gitignore @@ -0,0 +1 @@ +platform/ diff --git a/target/w3d_de1soc/intc.sv b/target/w3d_de1soc/intc.sv new file mode 100644 index 0000000..af78ef8 --- /dev/null +++ b/target/w3d_de1soc/intc.sv @@ -0,0 +1,30 @@ +module intc +( + input logic clk, + rst_n, + + input logic irq_timer, + irq_jtaguart, + + input logic avl_address, + avl_read, + avl_write, + input logic[31:0] avl_writedata, + + output logic avl_irq, + output logic[31:0] avl_readdata +); + + logic[31:0] status, mask; + + assign status = {30'b0, irq_jtaguart, irq_timer} & mask; + assign avl_irq = |status; + assign avl_readdata = avl_address ? mask : status; + + always @(posedge clk or negedge rst_n) + if(!rst_n) + mask <= 0; + else if(avl_write && avl_address) + mask <= avl_writedata; + +endmodule diff --git a/target/w3d_de1soc/intc_hw.tcl b/target/w3d_de1soc/intc_hw.tcl new file mode 100644 index 0000000..a306432 --- /dev/null +++ b/target/w3d_de1soc/intc_hw.tcl @@ -0,0 +1,168 @@ +# TCL File Generated by Component Editor 20.1 +# Thu Dec 15 09:41:45 GMT 2022 +# DO NOT MODIFY + + +# +# intc "Interrupt controller" v1.0 +# 2022.12.15.09:41:45 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module intc +# +set_module_property DESCRIPTION "" +set_module_property NAME intc +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME "Interrupt controller" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL intc +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file intc.sv SYSTEM_VERILOG PATH intc.sv TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock_sink +# +add_interface clock_sink clock end +set_interface_property clock_sink clockRate 0 +set_interface_property clock_sink ENABLED true +set_interface_property clock_sink EXPORT_OF "" +set_interface_property clock_sink PORT_NAME_MAP "" +set_interface_property clock_sink CMSIS_SVD_VARIABLES "" +set_interface_property clock_sink SVD_ADDRESS_GROUP "" + +add_interface_port clock_sink clk clk Input 1 + + +# +# connection point reset_sink +# +add_interface reset_sink reset end +set_interface_property reset_sink associatedClock clock_sink +set_interface_property reset_sink synchronousEdges DEASSERT +set_interface_property reset_sink ENABLED true +set_interface_property reset_sink EXPORT_OF "" +set_interface_property reset_sink PORT_NAME_MAP "" +set_interface_property reset_sink CMSIS_SVD_VARIABLES "" +set_interface_property reset_sink SVD_ADDRESS_GROUP "" + +add_interface_port reset_sink rst_n reset_n Input 1 + + +# +# connection point avalon_slave +# +add_interface avalon_slave avalon end +set_interface_property avalon_slave addressUnits WORDS +set_interface_property avalon_slave associatedClock clock_sink +set_interface_property avalon_slave associatedReset reset_sink +set_interface_property avalon_slave bitsPerSymbol 8 +set_interface_property avalon_slave burstOnBurstBoundariesOnly false +set_interface_property avalon_slave burstcountUnits WORDS +set_interface_property avalon_slave explicitAddressSpan 0 +set_interface_property avalon_slave holdTime 0 +set_interface_property avalon_slave linewrapBursts false +set_interface_property avalon_slave maximumPendingReadTransactions 0 +set_interface_property avalon_slave maximumPendingWriteTransactions 0 +set_interface_property avalon_slave readLatency 0 +set_interface_property avalon_slave readWaitTime 1 +set_interface_property avalon_slave setupTime 0 +set_interface_property avalon_slave timingUnits Cycles +set_interface_property avalon_slave writeWaitTime 0 +set_interface_property avalon_slave ENABLED true +set_interface_property avalon_slave EXPORT_OF "" +set_interface_property avalon_slave PORT_NAME_MAP "" +set_interface_property avalon_slave CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave SVD_ADDRESS_GROUP "" + +add_interface_port avalon_slave avl_address address Input 1 +add_interface_port avalon_slave avl_read read Input 1 +add_interface_port avalon_slave avl_write write Input 1 +add_interface_port avalon_slave avl_readdata readdata Output 32 +add_interface_port avalon_slave avl_writedata writedata Input 32 +set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point interrupt_sender +# +add_interface interrupt_sender interrupt end +set_interface_property interrupt_sender associatedAddressablePoint avalon_slave +set_interface_property interrupt_sender associatedClock clock_sink +set_interface_property interrupt_sender bridgedReceiverOffset "" +set_interface_property interrupt_sender bridgesToReceiver "" +set_interface_property interrupt_sender ENABLED true +set_interface_property interrupt_sender EXPORT_OF "" +set_interface_property interrupt_sender PORT_NAME_MAP "" +set_interface_property interrupt_sender CMSIS_SVD_VARIABLES "" +set_interface_property interrupt_sender SVD_ADDRESS_GROUP "" + +add_interface_port interrupt_sender avl_irq irq Output 1 + + +# +# connection point interrupt_timer +# +add_interface interrupt_timer interrupt start +set_interface_property interrupt_timer associatedAddressablePoint "" +set_interface_property interrupt_timer associatedClock clock_sink +set_interface_property interrupt_timer irqScheme INDIVIDUAL_REQUESTS +set_interface_property interrupt_timer ENABLED true +set_interface_property interrupt_timer EXPORT_OF "" +set_interface_property interrupt_timer PORT_NAME_MAP "" +set_interface_property interrupt_timer CMSIS_SVD_VARIABLES "" +set_interface_property interrupt_timer SVD_ADDRESS_GROUP "" + +add_interface_port interrupt_timer irq_timer irq Input 1 + + +# +# connection point interrupt_jtaguart +# +add_interface interrupt_jtaguart interrupt start +set_interface_property interrupt_jtaguart associatedAddressablePoint "" +set_interface_property interrupt_jtaguart associatedClock clock_sink +set_interface_property interrupt_jtaguart irqScheme INDIVIDUAL_REQUESTS +set_interface_property interrupt_jtaguart ENABLED true +set_interface_property interrupt_jtaguart EXPORT_OF "" +set_interface_property interrupt_jtaguart PORT_NAME_MAP "" +set_interface_property interrupt_jtaguart CMSIS_SVD_VARIABLES "" +set_interface_property interrupt_jtaguart SVD_ADDRESS_GROUP "" + +add_interface_port interrupt_jtaguart irq_jtaguart irq Input 1 + diff --git a/target/w3d_de1soc/mod.mk b/target/w3d_de1soc/mod.mk new file mode 100644 index 0000000..a4aa4fe --- /dev/null +++ b/target/w3d_de1soc/mod.mk @@ -0,0 +1,14 @@ +define core + $(this)/deps := debounce axixbar wavelet3d + + $(this)/rtl_top := w3d_de1soc + $(this)/rtl_files := w3d_de1soc.sv + + $(this)/sdc_files := timing.sdc + $(this)/qip_files := $(patsubst %,../../ip/%.qip,dsp_mul ip_fp_add ip_fp_mul ip_fp_fix) + $(this)/qsf_files := pins.tcl + $(this)/qsys_platform := platform.qsys + + $(this)/altera_device := 5CSEMA5F31C6 + $(this)/altera_family := Cyclone V +endef diff --git a/target/w3d_de1soc/pins.tcl b/target/w3d_de1soc/pins.tcl new file mode 100644 index 0000000..5b7c3d7 --- /dev/null +++ b/target/w3d_de1soc/pins.tcl @@ -0,0 +1,185 @@ +set_instance_assignment -name D5_DELAY 2 -to memory_mem_ck -tag __hps_sdram_p0 +set_instance_assignment -name D5_DELAY 2 -to memory_mem_ck_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[4] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[5] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[6] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dq[7] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dm -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_dqs_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[10] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[11] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[12] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[3] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[4] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[5] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[6] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[7] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[8] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_a[9] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ba[0] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ba[1] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ba[2] -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_cas_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_cke -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_cs_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_odt -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ras_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_we_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_reset_n -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ck -tag __hps_sdram_p0 +set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to memory_mem_ck_n -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -tag __hps_sdram_p0 +set_instance_assignment -name GLOBAL_SIGNAL OFF -to plat|hps_0|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __hps_sdram_p0 +set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to plat|hps_0|hps_io|border|hps_sdram_inst -tag __hps_sdram_p0 +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to plat|hps_0|hps_io|border|hps_sdram_inst|pll0|fbout -tag __hps_sdram_p0 +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN ON +set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name ECO_REGENERATE_REPORT ON + + +set_location_assignment PIN_AF14 -to clk_clk +set_location_assignment PIN_AB12 -to rst_n + +set_location_assignment PIN_V16 -to pio_leds[0] +set_location_assignment PIN_W16 -to pio_leds[1] +set_location_assignment PIN_V17 -to pio_leds[2] +set_location_assignment PIN_V18 -to pio_leds[3] +set_location_assignment PIN_W17 -to pio_leds[4] +set_location_assignment PIN_W19 -to pio_leds[5] +set_location_assignment PIN_Y19 -to pio_leds[6] +set_location_assignment PIN_W20 -to pio_leds[7] + +set_location_assignment PIN_AA14 -to pio_buttons + +set_location_assignment PIN_AD11 -to pio_switches[0] +set_location_assignment PIN_AD12 -to pio_switches[1] +set_location_assignment PIN_AE11 -to pio_switches[2] +set_location_assignment PIN_AC9 -to pio_switches[3] +set_location_assignment PIN_AD10 -to pio_switches[4] +set_location_assignment PIN_AE12 -to pio_switches[5] + +set_location_assignment PIN_A11 -to vga_dac_clk +set_location_assignment PIN_B11 -to vga_dac_hsync +set_location_assignment PIN_D11 -to vga_dac_vsync +set_location_assignment PIN_F10 -to vga_dac_blank_n +set_location_assignment PIN_C10 -to vga_dac_sync_n +set_location_assignment PIN_A13 -to vga_dac_r[0] +set_location_assignment PIN_C13 -to vga_dac_r[1] +set_location_assignment PIN_E13 -to vga_dac_r[2] +set_location_assignment PIN_B12 -to vga_dac_r[3] +set_location_assignment PIN_C12 -to vga_dac_r[4] +set_location_assignment PIN_D12 -to vga_dac_r[5] +set_location_assignment PIN_E12 -to vga_dac_r[6] +set_location_assignment PIN_F13 -to vga_dac_r[7] +set_location_assignment PIN_J9 -to vga_dac_g[0] +set_location_assignment PIN_J10 -to vga_dac_g[1] +set_location_assignment PIN_H12 -to vga_dac_g[2] +set_location_assignment PIN_G10 -to vga_dac_g[3] +set_location_assignment PIN_G11 -to vga_dac_g[4] +set_location_assignment PIN_G12 -to vga_dac_g[5] +set_location_assignment PIN_F11 -to vga_dac_g[6] +set_location_assignment PIN_E11 -to vga_dac_g[7] +set_location_assignment PIN_B13 -to vga_dac_b[0] +set_location_assignment PIN_G13 -to vga_dac_b[1] +set_location_assignment PIN_H13 -to vga_dac_b[2] +set_location_assignment PIN_F14 -to vga_dac_b[3] +set_location_assignment PIN_H14 -to vga_dac_b[4] +set_location_assignment PIN_F15 -to vga_dac_b[5] +set_location_assignment PIN_G15 -to vga_dac_b[6] +set_location_assignment PIN_J14 -to vga_dac_b[7] + +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_oct_rzqin -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[0] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[0] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[0] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[1] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[1] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[1] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[2] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[2] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[2] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[3] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[3] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[3] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[4] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[4] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[4] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[5] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[5] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[5] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[6] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[6] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[6] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[7] -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[7] -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dq[7] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_dqs_n -tag __hps_sdram_p0 +set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dqs_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_ck -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to memory_mem_ck -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to memory_mem_ck_n -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to memory_mem_ck_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[0] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[0] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[10] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[10] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[11] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[11] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[12] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[12] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[1] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[1] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[2] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[2] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[3] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[3] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[4] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[4] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[5] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[5] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[6] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[6] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[7] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[7] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[8] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[8] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_a[9] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_a[9] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ba[0] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[0] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ba[1] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[1] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ba[2] -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ba[2] -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_cas_n -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cas_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_cke -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cke -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_cs_n -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_cs_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_odt -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_odt -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_ras_n -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_ras_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_we_n -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_we_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_reset_n -tag __hps_sdram_p0 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_reset_n -tag __hps_sdram_p0 +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dm -tag __hps_sdram_p0 +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dm -tag __hps_sdram_p0 diff --git a/target/w3d_de1soc/platform.qsys b/target/w3d_de1soc/platform.qsys new file mode 100644 index 0000000..1c0803e --- /dev/null +++ b/target/w3d_de1soc/platform.qsys @@ -0,0 +1,1600 @@ +<?xml version="1.0" encoding="UTF-8"?> +<system name="$${FILENAME}"> + <component + name="$${FILENAME}" + displayName="$${FILENAME}" + version="1.0" + description="" + tags="" + categories="System" /> + <parameter name="bonusData"><![CDATA[bonusData +{ + element buttons + { + datum _sortIndex + { + value = "11"; + type = "int"; + } + } + element clk_0 + { + datum _sortIndex + { + value = "0"; + type = "int"; + } + } + element dram_axi_bridge + { + datum _sortIndex + { + value = "17"; + type = "int"; + } + } + element hps_0 + { + datum _sortIndex + { + value = "1"; + type = "int"; + } + } + element intc_0 + { + datum _sortIndex + { + value = "12"; + type = "int"; + } + } + element io_axi_bridge + { + datum _sortIndex + { + value = "15"; + type = "int"; + } + } + element jtag_dbg + { + datum _sortIndex + { + value = "6"; + type = "int"; + } + } + element jtag_uart_0 + { + datum _sortIndex + { + value = "3"; + type = "int"; + } + } + element mm_bridge + { + datum _sortIndex + { + value = "13"; + type = "int"; + } + } + element pio_0 + { + datum _sortIndex + { + value = "5"; + type = "int"; + } + } + element pixfifo + { + datum _sortIndex + { + value = "9"; + type = "int"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element pll_0 + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } + element switches + { + datum _sortIndex + { + value = "10"; + type = "int"; + } + } + element sys_clock + { + datum _sortIndex + { + value = "14"; + type = "int"; + } + } + element sys_rst + { + datum _sortIndex + { + value = "16"; + type = "int"; + } + } + element timer_0 + { + datum _sortIndex + { + value = "4"; + type = "int"; + } + } + element vga + { + datum _sortIndex + { + value = "8"; + type = "int"; + } + datum sopceditor_expanded + { + value = "1"; + type = "boolean"; + } + } + element video_pll_0 + { + datum _sortIndex + { + value = "7"; + type = "int"; + } + } +} +]]></parameter> + <parameter name="clockCrossingAdapter" value="HANDSHAKE" /> + <parameter name="device" value="5CSEMA5F31C6" /> + <parameter name="deviceFamily" value="Cyclone V" /> + <parameter name="deviceSpeedGrade" value="6" /> + <parameter name="fabricMode" value="QSYS" /> + <parameter name="generateLegacySim" value="false" /> + <parameter name="generationId" value="0" /> + <parameter name="globalResetBus" value="false" /> + <parameter name="hdlLanguage" value="VERILOG" /> + <parameter name="hideFromIPCatalog" value="false" /> + <parameter name="lockedInterfaceDefinition" value="" /> + <parameter name="maxAdditionalLatency" value="1" /> + <parameter name="projectName" value="" /> + <parameter name="sopcBorderPoints" value="false" /> + <parameter name="systemHash" value="0" /> + <parameter name="testBenchDutName" value="" /> + <parameter name="timeStamp" value="0" /> + <parameter name="useTestBenchNamingPattern" value="false" /> + <instanceScript></instanceScript> + <interface + name="buttons_external_connection" + internal="buttons.external_connection" + type="conduit" + dir="end" /> + <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" /> + <interface + name="dram_axi_bridge_s0" + internal="dram_axi_bridge.s0" + type="axi4" + dir="end" /> + <interface + name="intc_0_interrupt_sender" + internal="intc_0.interrupt_sender" + type="interrupt" + dir="end" /> + <interface + name="io_axi_bridge_s0" + internal="io_axi_bridge.s0" + type="axi4" + dir="end" /> + <interface name="memory" internal="hps_0.memory" type="conduit" dir="end" /> + <interface + name="pio_0_external_connection" + internal="pio_0.external_connection" + type="conduit" + dir="end" /> + <interface + name="pixfifo_avalon_dc_buffer_sink" + internal="pixfifo.avalon_dc_buffer_sink" + type="avalon_streaming" + dir="end" /> + <interface name="pll_0_outclk3" internal="pll_0.outclk3" /> + <interface name="pll_0_reset" internal="pll_0.reset" type="reset" dir="end" /> + <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" /> + <interface + name="switches_external_connection" + internal="switches.external_connection" + type="conduit" + dir="end" /> + <interface + name="sys_clock_out_clk_1" + internal="sys_clock.out_clk_1" + type="clock" + dir="start" /> + <interface + name="sys_rst_out_reset_1" + internal="sys_rst.out_reset_1" + type="reset" + dir="start" /> + <interface + name="vga_dac" + internal="vga.external_interface" + type="conduit" + dir="end" /> + <module name="buttons" kind="altera_avalon_pio" version="20.1" enabled="1"> + <parameter name="bitClearingEdgeCapReg" value="false" /> + <parameter name="bitModifyingOutReg" value="false" /> + <parameter name="captureEdge" value="false" /> + <parameter name="clockRate" value="120000000" /> + <parameter name="direction" value="Input" /> + <parameter name="edgeType" value="RISING" /> + <parameter name="generateIRQ" value="false" /> + <parameter name="irqType" value="LEVEL" /> + <parameter name="resetValue" value="0" /> + <parameter name="simDoTestBenchWiring" value="false" /> + <parameter name="simDrivenValue" value="0" /> + <parameter name="width" value="8" /> + </module> + <module name="clk_0" kind="clock_source" version="20.1" enabled="1"> + <parameter name="clockFrequency" value="50000000" /> + <parameter name="clockFrequencyKnown" value="true" /> + <parameter name="inputClockFrequency" value="0" /> + <parameter name="resetSynchronousEdges" value="NONE" /> + </module> + <module + name="dram_axi_bridge" + kind="altera_axi_bridge" + version="20.1" + enabled="1"> + <parameter name="ADDR_WIDTH" value="32" /> + <parameter name="AXI_VERSION" value="AXI4" /> + <parameter name="COMBINED_ACCEPTANCE_CAPABILITY" value="16" /> + <parameter name="COMBINED_ISSUING_CAPABILITY" value="16" /> + <parameter name="DATA_WIDTH" value="32" /> + <parameter name="M0_ID_WIDTH" value="8" /> + <parameter name="READ_ACCEPTANCE_CAPABILITY" value="16" /> + <parameter name="READ_ADDR_USER_WIDTH" value="1" /> + <parameter name="READ_DATA_REORDERING_DEPTH" value="1" /> + <parameter name="READ_DATA_USER_WIDTH" value="1" /> + <parameter name="READ_ISSUING_CAPABILITY" value="16" /> + <parameter name="S0_ID_WIDTH" value="8" /> + <parameter name="USE_M0_ARBURST" value="1" /> + <parameter name="USE_M0_ARCACHE" value="1" /> + <parameter name="USE_M0_ARID" value="1" /> + <parameter name="USE_M0_ARLEN" value="1" /> + <parameter name="USE_M0_ARLOCK" value="1" /> + <parameter name="USE_M0_ARQOS" value="0" /> + <parameter name="USE_M0_ARREGION" value="1" /> + <parameter name="USE_M0_ARSIZE" value="1" /> + <parameter name="USE_M0_ARUSER" value="0" /> + <parameter name="USE_M0_AWBURST" value="1" /> + <parameter name="USE_M0_AWCACHE" value="1" /> + <parameter name="USE_M0_AWID" value="1" /> + <parameter name="USE_M0_AWLEN" value="1" /> + <parameter name="USE_M0_AWLOCK" value="1" /> + <parameter name="USE_M0_AWQOS" value="0" /> + <parameter name="USE_M0_AWREGION" value="0" /> + <parameter name="USE_M0_AWSIZE" value="1" /> + <parameter name="USE_M0_AWUSER" value="0" /> + <parameter name="USE_M0_BID" value="1" /> + <parameter name="USE_M0_BRESP" value="1" /> + <parameter name="USE_M0_BUSER" value="0" /> + <parameter name="USE_M0_RID" value="1" /> + <parameter name="USE_M0_RLAST" value="1" /> + <parameter name="USE_M0_RRESP" value="1" /> + <parameter name="USE_M0_RUSER" value="0" /> + <parameter name="USE_M0_WSTRB" value="1" /> + <parameter name="USE_M0_WUSER" value="0" /> + <parameter name="USE_PIPELINE" value="1" /> + <parameter name="USE_S0_ARCACHE" value="0" /> + <parameter name="USE_S0_ARLOCK" value="0" /> + <parameter name="USE_S0_ARPROT" value="0" /> + <parameter name="USE_S0_ARQOS" value="0" /> + <parameter name="USE_S0_ARREGION" value="0" /> + <parameter name="USE_S0_ARUSER" value="0" /> + <parameter name="USE_S0_AWCACHE" value="0" /> + <parameter name="USE_S0_AWLOCK" value="0" /> + <parameter name="USE_S0_AWPROT" value="0" /> + <parameter name="USE_S0_AWQOS" value="0" /> + <parameter name="USE_S0_AWREGION" value="0" /> + <parameter name="USE_S0_AWUSER" value="0" /> + <parameter name="USE_S0_BRESP" value="1" /> + <parameter name="USE_S0_BUSER" value="0" /> + <parameter name="USE_S0_RRESP" value="1" /> + <parameter name="USE_S0_RUSER" value="0" /> + <parameter name="USE_S0_WLAST" value="1" /> + <parameter name="USE_S0_WUSER" value="0" /> + <parameter name="WRITE_ACCEPTANCE_CAPABILITY" value="16" /> + <parameter name="WRITE_ADDR_USER_WIDTH" value="1" /> + <parameter name="WRITE_DATA_USER_WIDTH" value="1" /> + <parameter name="WRITE_ISSUING_CAPABILITY" value="16" /> + <parameter name="WRITE_RESP_USER_WIDTH" value="1" /> + </module> + <module name="hps_0" kind="altera_hps" version="20.1" enabled="1"> + <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" /> + <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" /> + <parameter name="ACV_PHY_CLK_ADD_FR_PHASE" value="0.0" /> + <parameter name="AC_PACKAGE_DESKEW" value="false" /> + <parameter name="AC_ROM_USER_ADD_0" value="0_0000_0000_0000" /> + <parameter name="AC_ROM_USER_ADD_1" value="0_0000_0000_1000" /> + <parameter name="ADDR_ORDER" value="0" /> + <parameter name="ADD_EFFICIENCY_MONITOR" value="false" /> + <parameter name="ADD_EXTERNAL_SEQ_DEBUG_NIOS" value="false" /> + <parameter name="ADVANCED_CK_PHASES" value="false" /> + <parameter name="ADVERTIZE_SEQUENCER_SW_BUILD_FILES" value="false" /> + <parameter name="AFI_DEBUG_INFO_WIDTH" value="32" /> + <parameter name="ALTMEMPHY_COMPATIBLE_MODE" value="false" /> + <parameter name="AP_MODE" value="false" /> + <parameter name="AP_MODE_EN" value="0" /> + <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" /> + <parameter name="AUTO_PD_CYCLES" value="0" /> + <parameter name="AUTO_POWERDN_EN" value="false" /> + <parameter name="AVL_DATA_WIDTH_PORT" value="32,32,32,32,32,32" /> + <parameter name="AVL_MAX_SIZE" value="4" /> + <parameter name="BONDING_OUT_ENABLED" value="false" /> + <parameter name="BOOTFROMFPGA_Enable" value="false" /> + <parameter name="BSEL" value="1" /> + <parameter name="BSEL_EN" value="false" /> + <parameter name="BYTE_ENABLE" value="true" /> + <parameter name="C2P_WRITE_CLOCK_ADD_PHASE" value="0.0" /> + <parameter name="CALIBRATION_MODE" value="Skip" /> + <parameter name="CALIB_REG_WIDTH" value="8" /> + <parameter name="CAN0_Mode" value="N/A" /> + <parameter name="CAN0_PinMuxing" value="Unused" /> + <parameter name="CAN1_Mode" value="N/A" /> + <parameter name="CAN1_PinMuxing" value="Unused" /> + <parameter name="CFG_DATA_REORDERING_TYPE" value="INTER_BANK" /> + <parameter name="CFG_REORDER_DATA" value="true" /> + <parameter name="CFG_TCCD_NS" value="2.5" /> + <parameter name="COMMAND_PHASE" value="0.0" /> + <parameter name="CONTROLLER_LATENCY" value="5" /> + <parameter name="CORE_DEBUG_CONNECTION" value="EXPORT" /> + <parameter name="CPORT_TYPE_PORT">Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional</parameter> + <parameter name="CSEL" value="0" /> + <parameter name="CSEL_EN" value="false" /> + <parameter name="CTI_Enable" value="false" /> + <parameter name="CTL_AUTOPCH_EN" value="false" /> + <parameter name="CTL_CMD_QUEUE_DEPTH" value="8" /> + <parameter name="CTL_CSR_CONNECTION" value="INTERNAL_JTAG" /> + <parameter name="CTL_CSR_ENABLED" value="false" /> + <parameter name="CTL_CSR_READ_ONLY" value="1" /> + <parameter name="CTL_DEEP_POWERDN_EN" value="false" /> + <parameter name="CTL_DYNAMIC_BANK_ALLOCATION" value="false" /> + <parameter name="CTL_DYNAMIC_BANK_NUM" value="4" /> + <parameter name="CTL_ECC_AUTO_CORRECTION_ENABLED" value="false" /> + <parameter name="CTL_ECC_ENABLED" value="false" /> + <parameter name="CTL_ENABLE_BURST_INTERRUPT" value="false" /> + <parameter name="CTL_ENABLE_BURST_TERMINATE" value="false" /> + <parameter name="CTL_HRB_ENABLED" value="false" /> + <parameter name="CTL_LOOK_AHEAD_DEPTH" value="4" /> + <parameter name="CTL_SELF_REFRESH_EN" value="false" /> + <parameter name="CTL_USR_REFRESH_EN" value="false" /> + <parameter name="CTL_ZQCAL_EN" value="false" /> + <parameter name="CUT_NEW_FAMILY_TIMING" value="true" /> + <parameter name="DAT_DATA_WIDTH" value="32" /> + <parameter name="DEBUGAPB_Enable" value="false" /> + <parameter name="DEBUG_MODE" value="false" /> + <parameter name="DEVICE_DEPTH" value="1" /> + <parameter name="DEVICE_FAMILY_PARAM" value="" /> + <parameter name="DISABLE_CHILD_MESSAGING" value="false" /> + <parameter name="DISCRETE_FLY_BY" value="true" /> + <parameter name="DLL_SHARING_MODE" value="None" /> + <parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter> + <parameter name="DQS_DQSN_MODE" value="DIFFERENTIAL" /> + <parameter name="DQ_INPUT_REG_USE_CLKN" value="false" /> + <parameter name="DUPLICATE_AC" value="false" /> + <parameter name="ED_EXPORT_SEQ_DEBUG" value="false" /> + <parameter name="EMAC0_Mode" value="N/A" /> + <parameter name="EMAC0_PTP" value="false" /> + <parameter name="EMAC0_PinMuxing" value="Unused" /> + <parameter name="EMAC1_Mode" value="N/A" /> + <parameter name="EMAC1_PTP" value="false" /> + <parameter name="EMAC1_PinMuxing" value="Unused" /> + <parameter name="ENABLE_ABS_RAM_MEM_INIT" value="false" /> + <parameter name="ENABLE_BONDING" value="false" /> + <parameter name="ENABLE_BURST_MERGE" value="false" /> + <parameter name="ENABLE_CTRL_AVALON_INTERFACE" value="true" /> + <parameter name="ENABLE_DELAY_CHAIN_WRITE" value="false" /> + <parameter name="ENABLE_EMIT_BFM_MASTER" value="false" /> + <parameter name="ENABLE_EXPORT_SEQ_DEBUG_BRIDGE" value="false" /> + <parameter name="ENABLE_EXTRA_REPORTING" value="false" /> + <parameter name="ENABLE_ISS_PROBES" value="false" /> + <parameter name="ENABLE_NON_DESTRUCTIVE_CALIB" value="false" /> + <parameter name="ENABLE_NON_DES_CAL" value="false" /> + <parameter name="ENABLE_NON_DES_CAL_TEST" value="false" /> + <parameter name="ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT" value="false" /> + <parameter name="ENABLE_USER_ECC" value="false" /> + <parameter name="EXPORT_AFI_HALF_CLK" value="false" /> + <parameter name="EXTRA_SETTINGS" value="" /> + <parameter name="F2H_AXI_CLOCK_FREQ" value="100" /> + <parameter name="F2H_SDRAM0_CLOCK_FREQ" value="120000000" /> + <parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" /> + <parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" /> + <parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" /> + <parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" /> + <parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" /> + <parameter name="F2SCLK_COLDRST_Enable" value="false" /> + <parameter name="F2SCLK_DBGRST_Enable" value="false" /> + <parameter name="F2SCLK_PERIPHCLK_Enable" value="false" /> + <parameter name="F2SCLK_PERIPHCLK_FREQ" value="0" /> + <parameter name="F2SCLK_SDRAMCLK_Enable" value="false" /> + <parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" /> + <parameter name="F2SCLK_WARMRST_Enable" value="false" /> + <parameter name="F2SDRAM_Type" value="AXI-3" /> + <parameter name="F2SDRAM_Width" value="32" /> + <parameter name="F2SINTERRUPT_Enable" value="false" /> + <parameter name="F2S_Width" value="0" /> + <parameter name="FIX_READ_LATENCY" value="8" /> + <parameter name="FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT" value="false" /> + <parameter name="FORCED_NUM_WRITE_FR_CYCLE_SHIFTS" value="0" /> + <parameter name="FORCE_DQS_TRACKING" value="AUTO" /> + <parameter name="FORCE_MAX_LATENCY_COUNT_WIDTH" value="0" /> + <parameter name="FORCE_SEQUENCER_TCL_DEBUG_MODE" value="false" /> + <parameter name="FORCE_SHADOW_REGS" value="AUTO" /> + <parameter name="FORCE_SYNTHESIS_LANGUAGE" value="" /> + <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" /> + <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" /> + <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" /> + <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" /> + <parameter + name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK" + value="100" /> + <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="100" /> + <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" /> + <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C2_SCL_IN" value="100" /> + <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C3_SCL_IN" value="100" /> + <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" /> + <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" /> + <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" /> + <parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" /> + <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="125" /> + <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="2.5" /> + <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="125" /> + <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="2.5" /> + <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" /> + <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" /> + <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C2_CLK" value="100" /> + <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C3_CLK" value="100" /> + <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" /> + <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDIO_CCLK" value="100" /> + <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" /> + <parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" /> + <parameter name="GPIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter> + <parameter name="GP_Enable" value="false" /> + <parameter name="H2F_AXI_CLOCK_FREQ" value="100" /> + <parameter name="H2F_CTI_CLOCK_FREQ" value="100" /> + <parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" /> + <parameter name="H2F_LW_AXI_CLOCK_FREQ" value="100" /> + <parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" /> + <parameter name="HARD_EMIF" value="true" /> + <parameter name="HCX_COMPAT_MODE" value="false" /> + <parameter name="HHP_HPS" value="true" /> + <parameter name="HHP_HPS_SIMULATION" value="false" /> + <parameter name="HHP_HPS_VERIFICATION" value="false" /> + <parameter name="HLGPI_Enable" value="false" /> + <parameter name="HPS_PROTOCOL" value="DDR3" /> + <parameter name="I2C0_Mode" value="N/A" /> + <parameter name="I2C0_PinMuxing" value="Unused" /> + <parameter name="I2C1_Mode" value="N/A" /> + <parameter name="I2C1_PinMuxing" value="Unused" /> + <parameter name="I2C2_Mode" value="N/A" /> + <parameter name="I2C2_PinMuxing" value="Unused" /> + <parameter name="I2C3_Mode" value="N/A" /> + <parameter name="I2C3_PinMuxing" value="Unused" /> + <parameter name="INCLUDE_BOARD_DELAY_MODEL" value="false" /> + <parameter name="INCLUDE_MULTIRANK_BOARD_DELAY_MODEL" value="false" /> + <parameter name="IS_ES_DEVICE" value="false" /> + <parameter name="LOANIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter> + <parameter name="LOCAL_ID_WIDTH" value="8" /> + <parameter name="LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter> + <parameter name="LWH2F_Enable" value="false" /> + <parameter name="MARGIN_VARIATION_TEST" value="false" /> + <parameter name="MAX_PENDING_RD_CMD" value="32" /> + <parameter name="MAX_PENDING_WR_CMD" value="16" /> + <parameter name="MEM_ASR" value="Manual" /> + <parameter name="MEM_ATCL" value="Disabled" /> + <parameter name="MEM_AUTO_LEVELING_MODE" value="true" /> + <parameter name="MEM_BANKADDR_WIDTH" value="3" /> + <parameter name="MEM_BL" value="OTF" /> + <parameter name="MEM_BT" value="Sequential" /> + <parameter name="MEM_CK_PHASE" value="0.0" /> + <parameter name="MEM_CK_WIDTH" value="1" /> + <parameter name="MEM_CLK_EN_WIDTH" value="1" /> + <parameter name="MEM_CLK_FREQ" value="300.0" /> + <parameter name="MEM_CLK_FREQ_MAX" value="400.0" /> + <parameter name="MEM_COL_ADDR_WIDTH" value="8" /> + <parameter name="MEM_CS_WIDTH" value="1" /> + <parameter name="MEM_DEVICE" value="MISSING_MODEL" /> + <parameter name="MEM_DLL_EN" value="true" /> + <parameter name="MEM_DQ_PER_DQS" value="8" /> + <parameter name="MEM_DQ_WIDTH" value="8" /> + <parameter name="MEM_DRV_STR" value="RZQ/6" /> + <parameter name="MEM_FORMAT" value="DISCRETE" /> + <parameter name="MEM_GUARANTEED_WRITE_INIT" value="false" /> + <parameter name="MEM_IF_BOARD_BASE_DELAY" value="10" /> + <parameter name="MEM_IF_DM_PINS_EN" value="true" /> + <parameter name="MEM_IF_DQSN_EN" value="true" /> + <parameter name="MEM_IF_SIM_VALID_WINDOW" value="0" /> + <parameter name="MEM_INIT_EN" value="false" /> + <parameter name="MEM_INIT_FILE" value="" /> + <parameter name="MEM_MIRROR_ADDRESSING" value="0" /> + <parameter name="MEM_NUMBER_OF_DIMMS" value="1" /> + <parameter name="MEM_NUMBER_OF_RANKS_PER_DEVICE" value="1" /> + <parameter name="MEM_NUMBER_OF_RANKS_PER_DIMM" value="1" /> + <parameter name="MEM_PD" value="DLL off" /> + <parameter name="MEM_RANK_MULTIPLICATION_FACTOR" value="1" /> + <parameter name="MEM_ROW_ADDR_WIDTH" value="12" /> + <parameter name="MEM_RTT_NOM" value="ODT Disabled" /> + <parameter name="MEM_RTT_WR" value="Dynamic ODT off" /> + <parameter name="MEM_SRT" value="Normal" /> + <parameter name="MEM_TCL" value="7" /> + <parameter name="MEM_TFAW_NS" value="37.5" /> + <parameter name="MEM_TINIT_US" value="499" /> + <parameter name="MEM_TMRD_CK" value="3" /> + <parameter name="MEM_TRAS_NS" value="40.0" /> + <parameter name="MEM_TRCD_NS" value="15.0" /> + <parameter name="MEM_TREFI_US" value="7.0" /> + <parameter name="MEM_TRFC_NS" value="75.0" /> + <parameter name="MEM_TRP_NS" value="15.0" /> + <parameter name="MEM_TRRD_NS" value="7.5" /> + <parameter name="MEM_TRTP_NS" value="7.5" /> + <parameter name="MEM_TWR_NS" value="15.0" /> + <parameter name="MEM_TWTR" value="2" /> + <parameter name="MEM_USER_LEVELING_MODE" value="Leveling" /> + <parameter name="MEM_VENDOR" value="JEDEC" /> + <parameter name="MEM_VERBOSE" value="true" /> + <parameter name="MEM_VOLTAGE" value="1.5V DDR3" /> + <parameter name="MEM_WTCL" value="6" /> + <parameter name="MPU_EVENTS_Enable" value="false" /> + <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" /> + <parameter name="MULTICAST_EN" value="false" /> + <parameter name="NAND_Mode" value="N/A" /> + <parameter name="NAND_PinMuxing" value="Unused" /> + <parameter name="NEXTGEN" value="true" /> + <parameter name="NIOS_ROM_DATA_WIDTH" value="32" /> + <parameter name="NUM_DLL_SHARING_INTERFACES" value="1" /> + <parameter name="NUM_EXTRA_REPORT_PATH" value="10" /> + <parameter name="NUM_OCT_SHARING_INTERFACES" value="1" /> + <parameter name="NUM_OF_PORTS" value="1" /> + <parameter name="NUM_PLL_SHARING_INTERFACES" value="1" /> + <parameter name="OCT_SHARING_MODE" value="None" /> + <parameter name="P2C_READ_CLOCK_ADD_PHASE" value="0.0" /> + <parameter name="PACKAGE_DESKEW" value="false" /> + <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM" value="" /> + <parameter name="PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID" value="false" /> + <parameter name="PHY_CSR_CONNECTION" value="INTERNAL_JTAG" /> + <parameter name="PHY_CSR_ENABLED" value="false" /> + <parameter name="PHY_ONLY" value="false" /> + <parameter name="PINGPONGPHY_EN" value="false" /> + <parameter name="PLL_ADDR_CMD_CLK_DIV_PARAM" value="0" /> + <parameter name="PLL_ADDR_CMD_CLK_FREQ_PARAM" value="0.0" /> + <parameter name="PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM" value="" /> + <parameter name="PLL_ADDR_CMD_CLK_MULT_PARAM" value="0" /> + <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_PARAM" value="0" /> + <parameter name="PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> + <parameter name="PLL_AFI_CLK_DIV_PARAM" value="0" /> + <parameter name="PLL_AFI_CLK_FREQ_PARAM" value="0.0" /> + <parameter name="PLL_AFI_CLK_FREQ_SIM_STR_PARAM" value="" /> + <parameter name="PLL_AFI_CLK_MULT_PARAM" value="0" /> + <parameter name="PLL_AFI_CLK_PHASE_PS_PARAM" value="0" /> + <parameter name="PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> + <parameter name="PLL_AFI_HALF_CLK_DIV_PARAM" value="0" /> + <parameter name="PLL_AFI_HALF_CLK_FREQ_PARAM" value="0.0" /> + <parameter name="PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM" value="" /> + <parameter name="PLL_AFI_HALF_CLK_MULT_PARAM" value="0" /> + <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_PARAM" value="0" /> + <parameter name="PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> + <parameter name="PLL_AFI_PHY_CLK_DIV_PARAM" value="0" /> + <parameter name="PLL_AFI_PHY_CLK_FREQ_PARAM" value="0.0" /> + <parameter name="PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM" value="" /> + <parameter name="PLL_AFI_PHY_CLK_MULT_PARAM" value="0" /> + <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_PARAM" value="0" /> + <parameter name="PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> + <parameter name="PLL_C2P_WRITE_CLK_DIV_PARAM" value="0" /> + <parameter name="PLL_C2P_WRITE_CLK_FREQ_PARAM" value="0.0" /> + <parameter name="PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" /> + <parameter name="PLL_C2P_WRITE_CLK_MULT_PARAM" value="0" /> + <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_PARAM" value="0" /> + <parameter name="PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> + <parameter name="PLL_CLK_PARAM_VALID" value="false" /> + <parameter name="PLL_CONFIG_CLK_DIV_PARAM" value="0" /> + <parameter name="PLL_CONFIG_CLK_FREQ_PARAM" value="0.0" /> + <parameter name="PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM" value="" /> + <parameter name="PLL_CONFIG_CLK_MULT_PARAM" value="0" /> + <parameter name="PLL_CONFIG_CLK_PHASE_PS_PARAM" value="0" /> + <parameter name="PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> + <parameter name="PLL_DR_CLK_DIV_PARAM" value="0" /> + <parameter name="PLL_DR_CLK_FREQ_PARAM" value="0.0" /> + <parameter name="PLL_DR_CLK_FREQ_SIM_STR_PARAM" value="" /> + <parameter name="PLL_DR_CLK_MULT_PARAM" value="0" /> + <parameter name="PLL_DR_CLK_PHASE_PS_PARAM" value="0" /> + <parameter name="PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> + <parameter name="PLL_HR_CLK_DIV_PARAM" value="0" /> + <parameter name="PLL_HR_CLK_FREQ_PARAM" value="0.0" /> + <parameter name="PLL_HR_CLK_FREQ_SIM_STR_PARAM" value="" /> + <parameter name="PLL_HR_CLK_MULT_PARAM" value="0" /> + <parameter name="PLL_HR_CLK_PHASE_PS_PARAM" value="0" /> + <parameter name="PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> + <parameter name="PLL_LOCATION" value="Top_Bottom" /> + <parameter name="PLL_MEM_CLK_DIV_PARAM" value="0" /> + <parameter name="PLL_MEM_CLK_FREQ_PARAM" value="0.0" /> + <parameter name="PLL_MEM_CLK_FREQ_SIM_STR_PARAM" value="" /> + <parameter name="PLL_MEM_CLK_MULT_PARAM" value="0" /> + <parameter name="PLL_MEM_CLK_PHASE_PS_PARAM" value="0" /> + <parameter name="PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> + <parameter name="PLL_NIOS_CLK_DIV_PARAM" value="0" /> + <parameter name="PLL_NIOS_CLK_FREQ_PARAM" value="0.0" /> + <parameter name="PLL_NIOS_CLK_FREQ_SIM_STR_PARAM" value="" /> + <parameter name="PLL_NIOS_CLK_MULT_PARAM" value="0" /> + <parameter name="PLL_NIOS_CLK_PHASE_PS_PARAM" value="0" /> + <parameter name="PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> + <parameter name="PLL_P2C_READ_CLK_DIV_PARAM" value="0" /> + <parameter name="PLL_P2C_READ_CLK_FREQ_PARAM" value="0.0" /> + <parameter name="PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM" value="" /> + <parameter name="PLL_P2C_READ_CLK_MULT_PARAM" value="0" /> + <parameter name="PLL_P2C_READ_CLK_PHASE_PS_PARAM" value="0" /> + <parameter name="PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> + <parameter name="PLL_SHARING_MODE" value="None" /> + <parameter name="PLL_WRITE_CLK_DIV_PARAM" value="0" /> + <parameter name="PLL_WRITE_CLK_FREQ_PARAM" value="0.0" /> + <parameter name="PLL_WRITE_CLK_FREQ_SIM_STR_PARAM" value="" /> + <parameter name="PLL_WRITE_CLK_MULT_PARAM" value="0" /> + <parameter name="PLL_WRITE_CLK_PHASE_PS_PARAM" value="0" /> + <parameter name="PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM" value="" /> + <parameter name="POWER_OF_TWO_BUS" value="false" /> + <parameter name="PRIORITY_PORT" value="1,1,1,1,1,1" /> + <parameter name="QSPI_Mode" value="N/A" /> + <parameter name="QSPI_PinMuxing" value="Unused" /> + <parameter name="RATE" value="Full" /> + <parameter name="RDIMM_CONFIG" value="0000000000000000" /> + <parameter name="READ_DQ_DQS_CLOCK_SOURCE" value="INVERTED_DQS_BUS" /> + <parameter name="READ_FIFO_SIZE" value="8" /> + <parameter name="REFRESH_BURST_VALIDATION" value="false" /> + <parameter name="REFRESH_INTERVAL" value="15000" /> + <parameter name="REF_CLK_FREQ" value="125.0" /> + <parameter name="REF_CLK_FREQ_MAX_PARAM" value="0.0" /> + <parameter name="REF_CLK_FREQ_MIN_PARAM" value="0.0" /> + <parameter name="REF_CLK_FREQ_PARAM_VALID" value="false" /> + <parameter name="S2FCLK_COLDRST_Enable" value="false" /> + <parameter name="S2FCLK_PENDINGRST_Enable" value="false" /> + <parameter name="S2FCLK_USER0CLK_Enable" value="false" /> + <parameter name="S2FCLK_USER1CLK_Enable" value="false" /> + <parameter name="S2FCLK_USER1CLK_FREQ" value="100.0" /> + <parameter name="S2FCLK_USER2CLK" value="5" /> + <parameter name="S2FCLK_USER2CLK_Enable" value="false" /> + <parameter name="S2FCLK_USER2CLK_FREQ" value="100.0" /> + <parameter name="S2FINTERRUPT_CAN_Enable" value="false" /> + <parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" /> + <parameter name="S2FINTERRUPT_CTI_Enable" value="false" /> + <parameter name="S2FINTERRUPT_DMA_Enable" value="false" /> + <parameter name="S2FINTERRUPT_EMAC_Enable" value="false" /> + <parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" /> + <parameter name="S2FINTERRUPT_GPIO_Enable" value="false" /> + <parameter name="S2FINTERRUPT_I2CEMAC_Enable" value="false" /> + <parameter name="S2FINTERRUPT_I2CPERIPHERAL_Enable" value="false" /> + <parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" /> + <parameter name="S2FINTERRUPT_NAND_Enable" value="false" /> + <parameter name="S2FINTERRUPT_OSCTIMER_Enable" value="false" /> + <parameter name="S2FINTERRUPT_QSPI_Enable" value="false" /> + <parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" /> + <parameter name="S2FINTERRUPT_SPIMASTER_Enable" value="false" /> + <parameter name="S2FINTERRUPT_SPISLAVE_Enable" value="false" /> + <parameter name="S2FINTERRUPT_UART_Enable" value="false" /> + <parameter name="S2FINTERRUPT_USB_Enable" value="false" /> + <parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" /> + <parameter name="S2F_Width" value="0" /> + <parameter name="SDIO_Mode" value="N/A" /> + <parameter name="SDIO_PinMuxing" value="Unused" /> + <parameter name="SEQUENCER_TYPE" value="NIOS" /> + <parameter name="SEQ_MODE" value="0" /> + <parameter name="SKIP_MEM_INIT" value="true" /> + <parameter name="SOPC_COMPAT_RESET" value="false" /> + <parameter name="SPEED_GRADE" value="7" /> + <parameter name="SPIM0_Mode" value="N/A" /> + <parameter name="SPIM0_PinMuxing" value="Unused" /> + <parameter name="SPIM1_Mode" value="N/A" /> + <parameter name="SPIM1_PinMuxing" value="Unused" /> + <parameter name="SPIS0_Mode" value="N/A" /> + <parameter name="SPIS0_PinMuxing" value="Unused" /> + <parameter name="SPIS1_Mode" value="N/A" /> + <parameter name="SPIS1_PinMuxing" value="Unused" /> + <parameter name="STARVE_LIMIT" value="10" /> + <parameter name="STM_Enable" value="false" /> + <parameter name="SYS_INFO_DEVICE_FAMILY" value="Cyclone V" /> + <parameter name="TEST_Enable" value="false" /> + <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_H" value="0.0" /> + <parameter name="TIMING_BOARD_AC_EYE_REDUCTION_SU" value="0.0" /> + <parameter name="TIMING_BOARD_AC_SKEW" value="0.02" /> + <parameter name="TIMING_BOARD_AC_SLEW_RATE" value="1.0" /> + <parameter name="TIMING_BOARD_AC_TO_CK_SKEW" value="0.0" /> + <parameter name="TIMING_BOARD_CK_CKN_SLEW_RATE" value="2.0" /> + <parameter name="TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME" value="0.0" /> + <parameter name="TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME" value="0.0" /> + <parameter name="TIMING_BOARD_DERATE_METHOD" value="AUTO" /> + <parameter name="TIMING_BOARD_DQS_DQSN_SLEW_RATE" value="2.0" /> + <parameter name="TIMING_BOARD_DQ_EYE_REDUCTION" value="0.0" /> + <parameter name="TIMING_BOARD_DQ_SLEW_RATE" value="1.0" /> + <parameter name="TIMING_BOARD_DQ_TO_DQS_SKEW" value="0.0" /> + <parameter name="TIMING_BOARD_ISI_METHOD" value="AUTO" /> + <parameter name="TIMING_BOARD_MAX_CK_DELAY" value="0.6" /> + <parameter name="TIMING_BOARD_MAX_DQS_DELAY" value="0.6" /> + <parameter name="TIMING_BOARD_READ_DQ_EYE_REDUCTION" value="0.0" /> + <parameter name="TIMING_BOARD_SKEW_BETWEEN_DIMMS" value="0.05" /> + <parameter name="TIMING_BOARD_SKEW_BETWEEN_DQS" value="0.02" /> + <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MAX" value="0.01" /> + <parameter name="TIMING_BOARD_SKEW_CKDQS_DIMM_MIN" value="-0.01" /> + <parameter name="TIMING_BOARD_SKEW_WITHIN_DQS" value="0.02" /> + <parameter name="TIMING_BOARD_TDH" value="0.0" /> + <parameter name="TIMING_BOARD_TDS" value="0.0" /> + <parameter name="TIMING_BOARD_TIH" value="0.0" /> + <parameter name="TIMING_BOARD_TIS" value="0.0" /> + <parameter name="TIMING_TDH" value="125" /> + <parameter name="TIMING_TDQSCK" value="400" /> + <parameter name="TIMING_TDQSCKDL" value="1200" /> + <parameter name="TIMING_TDQSCKDM" value="900" /> + <parameter name="TIMING_TDQSCKDS" value="450" /> + <parameter name="TIMING_TDQSH" value="0.35" /> + <parameter name="TIMING_TDQSQ" value="120" /> + <parameter name="TIMING_TDQSS" value="0.25" /> + <parameter name="TIMING_TDS" value="50" /> + <parameter name="TIMING_TDSH" value="0.2" /> + <parameter name="TIMING_TDSS" value="0.2" /> + <parameter name="TIMING_TIH" value="250" /> + <parameter name="TIMING_TIS" value="175" /> + <parameter name="TIMING_TQH" value="0.38" /> + <parameter name="TIMING_TQHS" value="300" /> + <parameter name="TIMING_TQSH" value="0.38" /> + <parameter name="TPIUFPGA_Enable" value="false" /> + <parameter name="TPIUFPGA_alt" value="false" /> + <parameter name="TRACE_Mode" value="N/A" /> + <parameter name="TRACE_PinMuxing" value="Unused" /> + <parameter name="TRACKING_ERROR_TEST" value="false" /> + <parameter name="TRACKING_WATCH_TEST" value="false" /> + <parameter name="TREFI" value="35100" /> + <parameter name="TRFC" value="350" /> + <parameter name="UART0_Mode" value="N/A" /> + <parameter name="UART0_PinMuxing" value="Unused" /> + <parameter name="UART1_Mode" value="N/A" /> + <parameter name="UART1_PinMuxing" value="Unused" /> + <parameter name="USB0_Mode" value="N/A" /> + <parameter name="USB0_PinMuxing" value="Unused" /> + <parameter name="USB1_Mode" value="N/A" /> + <parameter name="USB1_PinMuxing" value="Unused" /> + <parameter name="USER_DEBUG_LEVEL" value="1" /> + <parameter name="USE_AXI_ADAPTOR" value="false" /> + <parameter name="USE_FAKE_PHY" value="false" /> + <parameter name="USE_MEM_CLK_FREQ" value="false" /> + <parameter name="USE_MM_ADAPTOR" value="true" /> + <parameter name="USE_SEQUENCER_BFM" value="false" /> + <parameter name="WEIGHT_PORT" value="0,0,0,0,0,0" /> + <parameter name="WRBUFFER_ADDR_WIDTH" value="6" /> + <parameter name="can0_clk_div" value="1" /> + <parameter name="can1_clk_div" value="1" /> + <parameter name="configure_advanced_parameters" value="false" /> + <parameter name="customize_device_pll_info" value="false" /> + <parameter name="dbctrl_stayosc1" value="true" /> + <parameter name="dbg_at_clk_div" value="0" /> + <parameter name="dbg_clk_div" value="1" /> + <parameter name="dbg_trace_clk_div" value="0" /> + <parameter name="desired_can0_clk_mhz" value="100.0" /> + <parameter name="desired_can1_clk_mhz" value="100.0" /> + <parameter name="desired_cfg_clk_mhz" value="100.0" /> + <parameter name="desired_emac0_clk_mhz" value="250.0" /> + <parameter name="desired_emac1_clk_mhz" value="250.0" /> + <parameter name="desired_gpio_db_clk_hz" value="32000" /> + <parameter name="desired_l4_mp_clk_mhz" value="100.0" /> + <parameter name="desired_l4_sp_clk_mhz" value="100.0" /> + <parameter name="desired_mpu_clk_mhz" value="800.0" /> + <parameter name="desired_nand_clk_mhz" value="12.5" /> + <parameter name="desired_qspi_clk_mhz" value="400.0" /> + <parameter name="desired_sdmmc_clk_mhz" value="200.0" /> + <parameter name="desired_spi_m_clk_mhz" value="200.0" /> + <parameter name="desired_usb_mp_clk_mhz" value="200.0" /> + <parameter name="device_name" value="5CSEMA5F31C6" /> + <parameter name="device_pll_info_manual">{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}</parameter> + <parameter name="eosc1_clk_mhz" value="25.0" /> + <parameter name="eosc2_clk_mhz" value="25.0" /> + <parameter name="gpio_db_clk_div" value="6249" /> + <parameter name="l3_mp_clk_div" value="1" /> + <parameter name="l3_sp_clk_div" value="1" /> + <parameter name="l4_mp_clk_div" value="1" /> + <parameter name="l4_mp_clk_source" value="1" /> + <parameter name="l4_sp_clk_div" value="1" /> + <parameter name="l4_sp_clk_source" value="1" /> + <parameter name="main_pll_c3" value="3" /> + <parameter name="main_pll_c4" value="3" /> + <parameter name="main_pll_c5" value="15" /> + <parameter name="main_pll_m" value="63" /> + <parameter name="main_pll_n" value="0" /> + <parameter name="nand_clk_source" value="2" /> + <parameter name="periph_pll_c0" value="3" /> + <parameter name="periph_pll_c1" value="3" /> + <parameter name="periph_pll_c2" value="1" /> + <parameter name="periph_pll_c3" value="19" /> + <parameter name="periph_pll_c4" value="4" /> + <parameter name="periph_pll_c5" value="9" /> + <parameter name="periph_pll_m" value="79" /> + <parameter name="periph_pll_n" value="1" /> + <parameter name="periph_pll_source" value="0" /> + <parameter name="qspi_clk_source" value="1" /> + <parameter name="quartus_ini_hps_emif_pll" value="false" /> + <parameter + name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces" + value="false" /> + <parameter name="quartus_ini_hps_ip_enable_bsel_csel" value="false" /> + <parameter + name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface" + value="false" /> + <parameter + name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces" + value="false" /> + <parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" /> + <parameter name="quartus_ini_hps_ip_f2sdram_bonding_out" value="false" /> + <parameter name="quartus_ini_hps_ip_fast_f2sdram_sim_model" value="false" /> + <parameter name="quartus_ini_hps_ip_suppress_sdram_synth" value="false" /> + <parameter name="sdmmc_clk_source" value="2" /> + <parameter name="show_advanced_parameters" value="false" /> + <parameter name="show_debug_info_as_warning_msg" value="false" /> + <parameter name="show_warning_as_error_msg" value="false" /> + <parameter name="spi_m_clk_div" value="0" /> + <parameter name="usb_mp_clk_div" value="0" /> + <parameter name="use_default_mpu_clk" value="true" /> + </module> + <module name="intc_0" kind="intc" version="1.0" enabled="1"> + <parameter name="AUTO_INTERRUPT_JTAGUART_INTERRUPTS_USED" value="1" /> + <parameter name="AUTO_INTERRUPT_TIMER_INTERRUPTS_USED" value="1" /> + </module> + <module + name="io_axi_bridge" + kind="altera_axi_bridge" + version="20.1" + enabled="1"> + <parameter name="ADDR_WIDTH" value="32" /> + <parameter name="AXI_VERSION" value="AXI4" /> + <parameter name="COMBINED_ACCEPTANCE_CAPABILITY" value="16" /> + <parameter name="COMBINED_ISSUING_CAPABILITY" value="16" /> + <parameter name="DATA_WIDTH" value="32" /> + <parameter name="M0_ID_WIDTH" value="8" /> + <parameter name="READ_ACCEPTANCE_CAPABILITY" value="16" /> + <parameter name="READ_ADDR_USER_WIDTH" value="1" /> + <parameter name="READ_DATA_REORDERING_DEPTH" value="1" /> + <parameter name="READ_DATA_USER_WIDTH" value="1" /> + <parameter name="READ_ISSUING_CAPABILITY" value="16" /> + <parameter name="S0_ID_WIDTH" value="8" /> + <parameter name="USE_M0_ARBURST" value="1" /> + <parameter name="USE_M0_ARCACHE" value="1" /> + <parameter name="USE_M0_ARID" value="1" /> + <parameter name="USE_M0_ARLEN" value="1" /> + <parameter name="USE_M0_ARLOCK" value="1" /> + <parameter name="USE_M0_ARQOS" value="1" /> + <parameter name="USE_M0_ARREGION" value="1" /> + <parameter name="USE_M0_ARSIZE" value="1" /> + <parameter name="USE_M0_ARUSER" value="0" /> + <parameter name="USE_M0_AWBURST" value="1" /> + <parameter name="USE_M0_AWCACHE" value="1" /> + <parameter name="USE_M0_AWID" value="1" /> + <parameter name="USE_M0_AWLEN" value="1" /> + <parameter name="USE_M0_AWLOCK" value="1" /> + <parameter name="USE_M0_AWQOS" value="1" /> + <parameter name="USE_M0_AWREGION" value="1" /> + <parameter name="USE_M0_AWSIZE" value="1" /> + <parameter name="USE_M0_AWUSER" value="0" /> + <parameter name="USE_M0_BID" value="1" /> + <parameter name="USE_M0_BRESP" value="1" /> + <parameter name="USE_M0_BUSER" value="0" /> + <parameter name="USE_M0_RID" value="1" /> + <parameter name="USE_M0_RLAST" value="1" /> + <parameter name="USE_M0_RRESP" value="1" /> + <parameter name="USE_M0_RUSER" value="0" /> + <parameter name="USE_M0_WSTRB" value="1" /> + <parameter name="USE_M0_WUSER" value="0" /> + <parameter name="USE_PIPELINE" value="1" /> + <parameter name="USE_S0_ARCACHE" value="1" /> + <parameter name="USE_S0_ARLOCK" value="1" /> + <parameter name="USE_S0_ARPROT" value="1" /> + <parameter name="USE_S0_ARQOS" value="1" /> + <parameter name="USE_S0_ARREGION" value="1" /> + <parameter name="USE_S0_ARUSER" value="0" /> + <parameter name="USE_S0_AWCACHE" value="1" /> + <parameter name="USE_S0_AWLOCK" value="1" /> + <parameter name="USE_S0_AWPROT" value="1" /> + <parameter name="USE_S0_AWQOS" value="1" /> + <parameter name="USE_S0_AWREGION" value="1" /> + <parameter name="USE_S0_AWUSER" value="0" /> + <parameter name="USE_S0_BRESP" value="1" /> + <parameter name="USE_S0_BUSER" value="0" /> + <parameter name="USE_S0_RRESP" value="1" /> + <parameter name="USE_S0_RUSER" value="0" /> + <parameter name="USE_S0_WLAST" value="1" /> + <parameter name="USE_S0_WUSER" value="0" /> + <parameter name="WRITE_ACCEPTANCE_CAPABILITY" value="16" /> + <parameter name="WRITE_ADDR_USER_WIDTH" value="1" /> + <parameter name="WRITE_DATA_USER_WIDTH" value="1" /> + <parameter name="WRITE_ISSUING_CAPABILITY" value="16" /> + <parameter name="WRITE_RESP_USER_WIDTH" value="1" /> + </module> + <module + name="jtag_dbg" + kind="altera_jtag_avalon_master" + version="20.1" + enabled="1"> + <parameter name="AUTO_DEVICE" value="5CSEMA5F31C6" /> + <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" /> + <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" /> + <parameter name="COMPONENT_CLOCK" value="0" /> + <parameter name="FAST_VER" value="0" /> + <parameter name="FIFO_DEPTHS" value="2" /> + <parameter name="PLI_PORT" value="50000" /> + <parameter name="USE_PLI" value="0" /> + </module> + <module + name="jtag_uart_0" + kind="altera_avalon_jtag_uart" + version="20.1" + enabled="1"> + <parameter name="allowMultipleConnections" value="false" /> + <parameter name="avalonSpec" value="2.0" /> + <parameter name="clkFreq" value="120000000" /> + <parameter name="hubInstanceID" value="0" /> + <parameter name="readBufferDepth" value="64" /> + <parameter name="readIRQThreshold" value="8" /> + <parameter name="simInputCharacterStream" value="" /> + <parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter> + <parameter name="useRegistersForReadBuffer" value="false" /> + <parameter name="useRegistersForWriteBuffer" value="false" /> + <parameter name="useRelativePathForSimFile" value="false" /> + <parameter name="writeBufferDepth" value="64" /> + <parameter name="writeIRQThreshold" value="8" /> + </module> + <module + name="mm_bridge" + kind="altera_avalon_mm_bridge" + version="20.1" + enabled="1"> + <parameter name="ADDRESS_UNITS" value="SYMBOLS" /> + <parameter name="ADDRESS_WIDTH" value="32" /> + <parameter name="DATA_WIDTH" value="128" /> + <parameter name="LINEWRAPBURSTS" value="0" /> + <parameter name="MAX_BURST_SIZE" value="1" /> + <parameter name="MAX_PENDING_RESPONSES" value="4" /> + <parameter name="PIPELINE_COMMAND" value="1" /> + <parameter name="PIPELINE_RESPONSE" value="1" /> + <parameter name="SYMBOL_WIDTH" value="8" /> + <parameter name="SYSINFO_ADDR_WIDTH" value="30" /> + <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" /> + <parameter name="USE_RESPONSE" value="0" /> + </module> + <module name="pio_0" kind="altera_avalon_pio" version="20.1" enabled="1"> + <parameter name="bitClearingEdgeCapReg" value="false" /> + <parameter name="bitModifyingOutReg" value="true" /> + <parameter name="captureEdge" value="false" /> + <parameter name="clockRate" value="120000000" /> + <parameter name="direction" value="Output" /> + <parameter name="edgeType" value="RISING" /> + <parameter name="generateIRQ" value="false" /> + <parameter name="irqType" value="LEVEL" /> + <parameter name="resetValue" value="0" /> + <parameter name="simDoTestBenchWiring" value="false" /> + <parameter name="simDrivenValue" value="0" /> + <parameter name="width" value="8" /> + </module> + <module + name="pixfifo" + kind="altera_up_avalon_video_dual_clock_buffer" + version="18.0" + enabled="1"> + <parameter name="AUTO_CLOCK_STREAM_IN_CLOCK_RATE" value="120000000" /> + <parameter name="AUTO_CLOCK_STREAM_OUT_CLOCK_RATE" value="25000000" /> + <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" /> + <parameter name="color_bits" value="10" /> + <parameter name="color_planes" value="3" /> + </module> + <module name="pll_0" kind="altera_pll" version="20.1" enabled="1"> + <parameter name="debug_print_output" value="false" /> + <parameter name="debug_use_rbc_taf_method" value="false" /> + <parameter name="device" value="5CSEMA5F31C6" /> + <parameter name="device_family" value="Cyclone V" /> + <parameter name="gui_active_clk" value="false" /> + <parameter name="gui_actual_output_clock_frequency0" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency1" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency10" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency11" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency12" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency13" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency14" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency15" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency16" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency17" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency2" value="120.000000 MHz" /> + <parameter name="gui_actual_output_clock_frequency3" value="25.396825 MHz" /> + <parameter name="gui_actual_output_clock_frequency4" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency5" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency6" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency7" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency8" value="0 MHz" /> + <parameter name="gui_actual_output_clock_frequency9" value="0 MHz" /> + <parameter name="gui_actual_phase_shift0" value="0" /> + <parameter name="gui_actual_phase_shift1" value="0" /> + <parameter name="gui_actual_phase_shift10" value="0" /> + <parameter name="gui_actual_phase_shift11" value="0" /> + <parameter name="gui_actual_phase_shift12" value="0" /> + <parameter name="gui_actual_phase_shift13" value="0" /> + <parameter name="gui_actual_phase_shift14" value="0" /> + <parameter name="gui_actual_phase_shift15" value="0" /> + <parameter name="gui_actual_phase_shift16" value="0" /> + <parameter name="gui_actual_phase_shift17" value="0" /> + <parameter name="gui_actual_phase_shift2" value="0" /> + <parameter name="gui_actual_phase_shift3" value="0" /> + <parameter name="gui_actual_phase_shift4" value="0" /> + <parameter name="gui_actual_phase_shift5" value="0" /> + <parameter name="gui_actual_phase_shift6" value="0" /> + <parameter name="gui_actual_phase_shift7" value="0" /> + <parameter name="gui_actual_phase_shift8" value="0" /> + <parameter name="gui_actual_phase_shift9" value="0" /> + <parameter name="gui_cascade_counter0" value="false" /> + <parameter name="gui_cascade_counter1" value="false" /> + <parameter name="gui_cascade_counter10" value="false" /> + <parameter name="gui_cascade_counter11" value="false" /> + <parameter name="gui_cascade_counter12" value="false" /> + <parameter name="gui_cascade_counter13" value="false" /> + <parameter name="gui_cascade_counter14" value="false" /> + <parameter name="gui_cascade_counter15" value="false" /> + <parameter name="gui_cascade_counter16" value="false" /> + <parameter name="gui_cascade_counter17" value="false" /> + <parameter name="gui_cascade_counter2" value="false" /> + <parameter name="gui_cascade_counter3" value="false" /> + <parameter name="gui_cascade_counter4" value="false" /> + <parameter name="gui_cascade_counter5" value="false" /> + <parameter name="gui_cascade_counter6" value="false" /> + <parameter name="gui_cascade_counter7" value="false" /> + <parameter name="gui_cascade_counter8" value="false" /> + <parameter name="gui_cascade_counter9" value="false" /> + <parameter name="gui_cascade_outclk_index" value="0" /> + <parameter name="gui_channel_spacing" value="0.0" /> + <parameter name="gui_clk_bad" value="false" /> + <parameter name="gui_device_speed_grade" value="1" /> + <parameter name="gui_divide_factor_c0" value="1" /> + <parameter name="gui_divide_factor_c1" value="1" /> + <parameter name="gui_divide_factor_c10" value="1" /> + <parameter name="gui_divide_factor_c11" value="1" /> + <parameter name="gui_divide_factor_c12" value="1" /> + <parameter name="gui_divide_factor_c13" value="1" /> + <parameter name="gui_divide_factor_c14" value="1" /> + <parameter name="gui_divide_factor_c15" value="1" /> + <parameter name="gui_divide_factor_c16" value="1" /> + <parameter name="gui_divide_factor_c17" value="1" /> + <parameter name="gui_divide_factor_c2" value="1" /> + <parameter name="gui_divide_factor_c3" value="1" /> + <parameter name="gui_divide_factor_c4" value="1" /> + <parameter name="gui_divide_factor_c5" value="1" /> + <parameter name="gui_divide_factor_c6" value="1" /> + <parameter name="gui_divide_factor_c7" value="1" /> + <parameter name="gui_divide_factor_c8" value="1" /> + <parameter name="gui_divide_factor_c9" value="1" /> + <parameter name="gui_divide_factor_n" value="1" /> + <parameter name="gui_dps_cntr" value="C0" /> + <parameter name="gui_dps_dir" value="Positive" /> + <parameter name="gui_dps_num" value="1" /> + <parameter name="gui_dsm_out_sel" value="1st_order" /> + <parameter name="gui_duty_cycle0" value="50" /> + <parameter name="gui_duty_cycle1" value="50" /> + <parameter name="gui_duty_cycle10" value="50" /> + <parameter name="gui_duty_cycle11" value="50" /> + <parameter name="gui_duty_cycle12" value="50" /> + <parameter name="gui_duty_cycle13" value="50" /> + <parameter name="gui_duty_cycle14" value="50" /> + <parameter name="gui_duty_cycle15" value="50" /> + <parameter name="gui_duty_cycle16" value="50" /> + <parameter name="gui_duty_cycle17" value="50" /> + <parameter name="gui_duty_cycle2" value="50" /> + <parameter name="gui_duty_cycle3" value="50" /> + <parameter name="gui_duty_cycle4" value="50" /> + <parameter name="gui_duty_cycle5" value="50" /> + <parameter name="gui_duty_cycle6" value="50" /> + <parameter name="gui_duty_cycle7" value="50" /> + <parameter name="gui_duty_cycle8" value="50" /> + <parameter name="gui_duty_cycle9" value="50" /> + <parameter name="gui_en_adv_params" value="false" /> + <parameter name="gui_en_dps_ports" value="false" /> + <parameter name="gui_en_phout_ports" value="false" /> + <parameter name="gui_en_reconf" value="false" /> + <parameter name="gui_enable_cascade_in" value="false" /> + <parameter name="gui_enable_cascade_out" value="false" /> + <parameter name="gui_enable_mif_dps" value="false" /> + <parameter name="gui_feedback_clock" value="Global Clock" /> + <parameter name="gui_frac_multiply_factor" value="1" /> + <parameter name="gui_fractional_cout" value="32" /> + <parameter name="gui_mif_generate" value="false" /> + <parameter name="gui_multiply_factor" value="1" /> + <parameter name="gui_number_of_clocks" value="1" /> + <parameter name="gui_operation_mode" value="direct" /> + <parameter name="gui_output_clock_frequency0" value="120.0" /> + <parameter name="gui_output_clock_frequency1" value="80.0" /> + <parameter name="gui_output_clock_frequency10" value="100.0" /> + <parameter name="gui_output_clock_frequency11" value="100.0" /> + <parameter name="gui_output_clock_frequency12" value="100.0" /> + <parameter name="gui_output_clock_frequency13" value="100.0" /> + <parameter name="gui_output_clock_frequency14" value="100.0" /> + <parameter name="gui_output_clock_frequency15" value="100.0" /> + <parameter name="gui_output_clock_frequency16" value="100.0" /> + <parameter name="gui_output_clock_frequency17" value="100.0" /> + <parameter name="gui_output_clock_frequency2" value="120.0" /> + <parameter name="gui_output_clock_frequency3" value="143.0" /> + <parameter name="gui_output_clock_frequency4" value="25.175" /> + <parameter name="gui_output_clock_frequency5" value="100.0" /> + <parameter name="gui_output_clock_frequency6" value="100.0" /> + <parameter name="gui_output_clock_frequency7" value="100.0" /> + <parameter name="gui_output_clock_frequency8" value="100.0" /> + <parameter name="gui_output_clock_frequency9" value="100.0" /> + <parameter name="gui_phase_shift0" value="0" /> + <parameter name="gui_phase_shift1" value="0" /> + <parameter name="gui_phase_shift10" value="0" /> + <parameter name="gui_phase_shift11" value="0" /> + <parameter name="gui_phase_shift12" value="0" /> + <parameter name="gui_phase_shift13" value="0" /> + <parameter name="gui_phase_shift14" value="0" /> + <parameter name="gui_phase_shift15" value="0" /> + <parameter name="gui_phase_shift16" value="0" /> + <parameter name="gui_phase_shift17" value="0" /> + <parameter name="gui_phase_shift2" value="0" /> + <parameter name="gui_phase_shift3" value="0" /> + <parameter name="gui_phase_shift4" value="0" /> + <parameter name="gui_phase_shift5" value="0" /> + <parameter name="gui_phase_shift6" value="0" /> + <parameter name="gui_phase_shift7" value="0" /> + <parameter name="gui_phase_shift8" value="0" /> + <parameter name="gui_phase_shift9" value="0" /> + <parameter name="gui_phase_shift_deg0" value="0.0" /> + <parameter name="gui_phase_shift_deg1" value="0.0" /> + <parameter name="gui_phase_shift_deg10" value="0.0" /> + <parameter name="gui_phase_shift_deg11" value="0.0" /> + <parameter name="gui_phase_shift_deg12" value="0.0" /> + <parameter name="gui_phase_shift_deg13" value="0.0" /> + <parameter name="gui_phase_shift_deg14" value="0.0" /> + <parameter name="gui_phase_shift_deg15" value="0.0" /> + <parameter name="gui_phase_shift_deg16" value="0.0" /> + <parameter name="gui_phase_shift_deg17" value="0.0" /> + <parameter name="gui_phase_shift_deg2" value="0.0" /> + <parameter name="gui_phase_shift_deg3" value="-50.0" /> + <parameter name="gui_phase_shift_deg4" value="0.0" /> + <parameter name="gui_phase_shift_deg5" value="0.0" /> + <parameter name="gui_phase_shift_deg6" value="0.0" /> + <parameter name="gui_phase_shift_deg7" value="0.0" /> + <parameter name="gui_phase_shift_deg8" value="0.0" /> + <parameter name="gui_phase_shift_deg9" value="0.0" /> + <parameter name="gui_phout_division" value="1" /> + <parameter name="gui_pll_auto_reset" value="On" /> + <parameter name="gui_pll_bandwidth_preset" value="Auto" /> + <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter> + <parameter name="gui_pll_mode" value="Fractional-N PLL" /> + <parameter name="gui_ps_units0" value="ps" /> + <parameter name="gui_ps_units1" value="ps" /> + <parameter name="gui_ps_units10" value="ps" /> + <parameter name="gui_ps_units11" value="ps" /> + <parameter name="gui_ps_units12" value="ps" /> + <parameter name="gui_ps_units13" value="ps" /> + <parameter name="gui_ps_units14" value="ps" /> + <parameter name="gui_ps_units15" value="ps" /> + <parameter name="gui_ps_units16" value="ps" /> + <parameter name="gui_ps_units17" value="ps" /> + <parameter name="gui_ps_units2" value="ps" /> + <parameter name="gui_ps_units3" value="degrees" /> + <parameter name="gui_ps_units4" value="ps" /> + <parameter name="gui_ps_units5" value="ps" /> + <parameter name="gui_ps_units6" value="ps" /> + <parameter name="gui_ps_units7" value="ps" /> + <parameter name="gui_ps_units8" value="ps" /> + <parameter name="gui_ps_units9" value="ps" /> + <parameter name="gui_refclk1_frequency" value="100.0" /> + <parameter name="gui_refclk_switch" value="false" /> + <parameter name="gui_reference_clock_frequency" value="50.0" /> + <parameter name="gui_switchover_delay" value="0" /> + <parameter name="gui_switchover_mode">Automatic Switchover</parameter> + <parameter name="gui_use_locked" value="false" /> + </module> + <module name="switches" kind="altera_avalon_pio" version="20.1" enabled="1"> + <parameter name="bitClearingEdgeCapReg" value="false" /> + <parameter name="bitModifyingOutReg" value="false" /> + <parameter name="captureEdge" value="false" /> + <parameter name="clockRate" value="120000000" /> + <parameter name="direction" value="Input" /> + <parameter name="edgeType" value="RISING" /> + <parameter name="generateIRQ" value="false" /> + <parameter name="irqType" value="LEVEL" /> + <parameter name="resetValue" value="0" /> + <parameter name="simDoTestBenchWiring" value="false" /> + <parameter name="simDrivenValue" value="0" /> + <parameter name="width" value="8" /> + </module> + <module + name="sys_clock" + kind="altera_clock_bridge" + version="20.1" + enabled="1"> + <parameter name="DERIVED_CLOCK_RATE" value="120000000" /> + <parameter name="EXPLICIT_CLOCK_RATE" value="0" /> + <parameter name="NUM_CLOCK_OUTPUTS" value="2" /> + </module> + <module name="sys_rst" kind="altera_reset_bridge" version="20.1" enabled="1"> + <parameter name="ACTIVE_LOW_RESET" value="1" /> + <parameter name="AUTO_CLK_CLOCK_RATE" value="120000000" /> + <parameter name="NUM_RESET_OUTPUTS" value="2" /> + <parameter name="SYNCHRONOUS_EDGES" value="deassert" /> + <parameter name="USE_RESET_REQUEST" value="0" /> + </module> + <module name="timer_0" kind="altera_avalon_timer" version="20.1" enabled="1"> + <parameter name="alwaysRun" value="false" /> + <parameter name="counterSize" value="32" /> + <parameter name="fixedPeriod" value="false" /> + <parameter name="period" value="1" /> + <parameter name="periodUnits" value="MSEC" /> + <parameter name="resetOutput" value="false" /> + <parameter name="snapshot" value="true" /> + <parameter name="systemFrequency" value="120000000" /> + <parameter name="timeoutPulseOutput" value="false" /> + <parameter name="watchdogPulse" value="2" /> + </module> + <module + name="vga" + kind="altera_up_avalon_video_vga_controller" + version="18.0" + enabled="1"> + <parameter name="AUTO_CLK_CLOCK_RATE" value="25000000" /> + <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" /> + <parameter name="board" value="DE1-SoC" /> + <parameter name="device" value="VGA Connector" /> + <parameter name="resolution" value="VGA 640x480" /> + <parameter name="underflow_flag" value="false" /> + </module> + <module + name="video_pll_0" + kind="altera_up_avalon_video_pll" + version="18.0" + enabled="1"> + <parameter name="AUTO_DEVICE" value="5CSEMA5F31C6" /> + <parameter name="AUTO_DEVICE_SPEEDGRADE" value="6" /> + <parameter name="camera">5MP Digital Camera (THDB_D5M)</parameter> + <parameter name="device_family" value="Cyclone V" /> + <parameter name="gui_refclk" value="50.0" /> + <parameter name="gui_resolution" value="VGA 640x480" /> + <parameter name="lcd">7" LCD on VEEK-MT and MTL/MTL2 Modules</parameter> + <parameter name="lcd_clk_en" value="false" /> + <parameter name="vga_clk_en" value="true" /> + <parameter name="video_in_clk_en" value="false" /> + </module> + <connection + kind="avalon" + version="20.1" + start="mm_bridge.m0" + end="jtag_uart_0.avalon_jtag_slave"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x30000000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection + kind="avalon" + version="20.1" + start="mm_bridge.m0" + end="intc_0.avalon_slave"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x30070000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection + kind="avalon" + version="20.1" + start="dram_axi_bridge.m0" + end="hps_0.f2h_sdram0_data"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection + kind="avalon" + version="20.1" + start="io_axi_bridge.m0" + end="mm_bridge.s0"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="buttons.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x30050000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="pio_0.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x30010000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="switches.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x30060000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="timer_0.s1"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x30020000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection + kind="avalon" + version="20.1" + start="jtag_dbg.master" + end="mm_bridge.s0"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection + kind="avalon_streaming" + version="20.1" + start="pixfifo.avalon_dc_buffer_source" + end="vga.avalon_vga_sink" /> + <connection + kind="clock" + version="20.1" + start="clk_0.clk" + end="video_pll_0.ref_clk" /> + <connection kind="clock" version="20.1" start="clk_0.clk" end="pll_0.refclk" /> + <connection + kind="clock" + version="20.1" + start="sys_clock.out_clk" + end="mm_bridge.clk" /> + <connection + kind="clock" + version="20.1" + start="sys_clock.out_clk" + end="buttons.clk" /> + <connection + kind="clock" + version="20.1" + start="sys_clock.out_clk" + end="switches.clk" /> + <connection + kind="clock" + version="20.1" + start="sys_clock.out_clk" + end="jtag_dbg.clk" /> + <connection kind="clock" version="20.1" start="sys_clock.out_clk" end="pio_0.clk" /> + <connection + kind="clock" + version="20.1" + start="sys_clock.out_clk" + end="timer_0.clk" /> + <connection + kind="clock" + version="20.1" + start="sys_clock.out_clk" + end="jtag_uart_0.clk" /> + <connection + kind="clock" + version="20.1" + start="sys_clock.out_clk" + end="io_axi_bridge.clk" /> + <connection + kind="clock" + version="20.1" + start="sys_clock.out_clk" + end="sys_rst.clk" /> + <connection + kind="clock" + version="20.1" + start="sys_clock.out_clk" + end="dram_axi_bridge.clk" /> + <connection + kind="clock" + version="20.1" + start="sys_clock.out_clk" + end="intc_0.clock_sink" /> + <connection + kind="clock" + version="20.1" + start="sys_clock.out_clk" + end="pixfifo.clock_stream_in" /> + <connection + kind="clock" + version="20.1" + start="sys_clock.out_clk" + end="hps_0.f2h_sdram0_clock" /> + <connection + kind="clock" + version="20.1" + start="pll_0.outclk0" + end="sys_clock.in_clk" /> + <connection kind="clock" version="20.1" start="video_pll_0.vga_clk" end="vga.clk" /> + <connection + kind="clock" + version="20.1" + start="video_pll_0.vga_clk" + end="pixfifo.clock_stream_out" /> + <connection + kind="interrupt" + version="20.1" + start="intc_0.interrupt_jtaguart" + end="jtag_uart_0.irq"> + <parameter name="irqNumber" value="0" /> + </connection> + <connection + kind="interrupt" + version="20.1" + start="intc_0.interrupt_timer" + end="timer_0.irq"> + <parameter name="irqNumber" value="0" /> + </connection> + <connection + kind="reset" + version="20.1" + start="clk_0.clk_reset" + end="sys_rst.in_reset" /> + <connection + kind="reset" + version="20.1" + start="sys_rst.out_reset" + end="io_axi_bridge.clk_reset" /> + <connection + kind="reset" + version="20.1" + start="sys_rst.out_reset" + end="jtag_dbg.clk_reset" /> + <connection + kind="reset" + version="20.1" + start="sys_rst.out_reset" + end="dram_axi_bridge.clk_reset" /> + <connection + kind="reset" + version="20.1" + start="sys_rst.out_reset" + end="video_pll_0.ref_reset" /> + <connection + kind="reset" + version="20.1" + start="sys_rst.out_reset" + end="jtag_uart_0.reset" /> + <connection + kind="reset" + version="20.1" + start="sys_rst.out_reset" + end="pio_0.reset" /> + <connection + kind="reset" + version="20.1" + start="sys_rst.out_reset" + end="switches.reset" /> + <connection + kind="reset" + version="20.1" + start="sys_rst.out_reset" + end="mm_bridge.reset" /> + <connection + kind="reset" + version="20.1" + start="sys_rst.out_reset" + end="timer_0.reset" /> + <connection + kind="reset" + version="20.1" + start="sys_rst.out_reset" + end="buttons.reset" /> + <connection + kind="reset" + version="20.1" + start="sys_rst.out_reset" + end="intc_0.reset_sink" /> + <connection + kind="reset" + version="20.1" + start="sys_rst.out_reset" + end="pixfifo.reset_stream_in" /> + <connection + kind="reset" + version="20.1" + start="video_pll_0.reset_source" + end="vga.reset" /> + <connection + kind="reset" + version="20.1" + start="video_pll_0.reset_source" + end="pixfifo.reset_stream_out" /> + <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> + <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" /> + <interconnectRequirement for="$system" name="qsys_mm.enableInstrumentation" value="FALSE" /> + <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> + <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" /> +</system> diff --git a/target/w3d_de1soc/timing.sdc b/target/w3d_de1soc/timing.sdc new file mode 100644 index 0000000..66d23f5 --- /dev/null +++ b/target/w3d_de1soc/timing.sdc @@ -0,0 +1,3 @@ +create_clock -period 20 -name clk_clk [get_ports clk_clk] +derive_pll_clocks +derive_clock_uncertainty diff --git a/target/w3d_de1soc/w3d_de1soc.sv b/target/w3d_de1soc/w3d_de1soc.sv new file mode 100644 index 0000000..65d0f4c --- /dev/null +++ b/target/w3d_de1soc/w3d_de1soc.sv @@ -0,0 +1,429 @@ +module w3d_de1soc +( + input wire clk_clk, + input wire rst_n, + + output wire [12:0] memory_mem_a, + output wire [2:0] memory_mem_ba, + output wire memory_mem_ck, + output wire memory_mem_ck_n, + output wire memory_mem_cke, + output wire memory_mem_cs_n, + output wire memory_mem_ras_n, + output wire memory_mem_cas_n, + output wire memory_mem_we_n, + output wire memory_mem_reset_n, + inout wire [7:0] memory_mem_dq, + inout wire memory_mem_dqs, + inout wire memory_mem_dqs_n, + output wire memory_mem_odt, + output wire memory_mem_dm, + input wire memory_oct_rzqin, + output wire [7:0] pio_leds, + input wire pio_buttons, + input wire [5:0] pio_switches, + output wire vga_dac_clk, + output wire vga_dac_hsync, + output wire vga_dac_vsync, + output wire vga_dac_blank_n, + output wire vga_dac_sync_n, + output wire [7:0] vga_dac_r, + output wire [7:0] vga_dac_g, + output wire [7:0] vga_dac_b +); + + logic button, reset_reset_n, sys_clk, sys_rst_n, sys_srst_n; + + logic dram_arready, dram_arvalid, dram_awready, dram_awvalid, dram_bready, dram_bvalid, + dram_rlast, dram_rready, dram_rvalid, dram_wlast, dram_wready, dram_wvalid; + + logic mmio_full_arready, mmio_full_arvalid, mmio_full_awready, mmio_full_awvalid, + mmio_full_bready, mmio_full_bvalid, mmio_full_rlast, mmio_full_rready, mmio_full_rvalid, + mmio_full_wlast, mmio_full_wready, mmio_full_wvalid; + + logic mmio_arready, mmio_arvalid, mmio_awready, mmio_awvalid, + mmio_bready, mmio_bvalid, mmio_rready, mmio_rvalid, + mmio_wready, mmio_wvalid; + + logic[1:0] dram_arburst, dram_awburst, dram_bresp, dram_rresp; + logic[2:0] dram_arsize, dram_awsize; + logic[3:0] dram_wstrb; + logic[7:0] dram_arid, dram_arlen, dram_awid, dram_awlen, dram_bid, dram_rid; + logic[31:0] dram_araddr, dram_awaddr, dram_rdata, dram_wdata; + + logic[7:0] mmio_full_arid, mmio_full_arlen, mmio_full_awid, mmio_full_awlen, + mmio_full_bid, mmio_full_rid; + + logic[1:0] mmio_full_arburst, mmio_full_awburst, mmio_full_bresp, mmio_full_rresp; + logic[2:0] mmio_full_arsize, mmio_full_awsize; + logic[3:0] mmio_full_arqos, mmio_full_awqos, mmio_full_wstrb; + logic[31:0] mmio_full_araddr, mmio_full_awaddr, mmio_full_rdata, mmio_full_wdata; + + logic[3:0] mmio_wstrb; + logic[31:0] mmio_araddr, mmio_awaddr, mmio_rdata, mmio_wdata; + + /*logic dram_axi3_arready, dram_axi3_arvalid, dram_axi3_awready, dram_axi3_awvalid, + dram_axi3_bready, dram_axi3_bvalid, dram_axi3_rlast, dram_axi3_rready, + dram_axi3_rvalid, dram_axi3_wlast, dram_axi3_wready, dram_axi3_wvalid; + + logic[1:0] dram_axi3_arburst, dram_axi3_arlock, dram_axi3_awburst, dram_axi3_awlock, + dram_axi3_bresp, dram_axi3_rresp; + + logic[3:0] dram_axi3_arcache, dram_axi3_arlen, ram_axi3_awcache, dram_axi3_awlen, + dram_axi3_wstrb; + + logic[2:0] dram_axi3_arprot, dram_axi3_arsize, dram_axi3_awprot, dram_axi3_awsize; + logic[7:0] dram_axi3_arid, dram_axi3_awid, dram_axi3_bid, dram_axi3_rid, dram_axi3_wid; + logic[31:0] dram_axi3_araddr, dram_axi3_awaddr, dram_axi3_rdata, dram_axi3_wdata;*/ + + logic mmio_full_arlock, mmio_full_awlock; + logic[2:0] mmio_full_arprot, mmio_full_awprot; + logic[3:0] mmio_full_arcache, mmio_full_awcache; + + debounce reset_debounce + ( + .clk(clk_clk), + .dirty(rst_n), + .clean(reset_reset_n) + ); + + debounce button_debounce + ( + .clk(clk_clk), + .dirty(pio_buttons), + .clean(button) + ); + + platform plat + ( + //FIXME: el glitch de reset + .clk_clk, + .reset_reset_n, + .pll_0_reset_reset(0), //TODO: reset controller, algún día + .memory_mem_a, + .memory_mem_ba, + .memory_mem_ck, + .memory_mem_ck_n, + .memory_mem_cke, + .memory_mem_cs_n, + .memory_mem_ras_n, + .memory_mem_cas_n, + .memory_mem_we_n, + .memory_mem_reset_n, + .memory_mem_dq, + .memory_mem_dqs, + .memory_mem_dqs_n, + .memory_mem_odt, + .memory_mem_dm, + .memory_oct_rzqin, + .pio_0_external_connection_export(pio_leds), + .buttons_external_connection_export({7'b0000000, !button}), + .switches_external_connection_export({2'b00, pio_switches}), + .vga_dac_CLK(vga_dac_clk), + .vga_dac_HS(vga_dac_hsync), + .vga_dac_VS(vga_dac_vsync), + .vga_dac_BLANK(vga_dac_blank_n), + .vga_dac_SYNC(vga_dac_sync_n), + .vga_dac_R(vga_dac_r), + .vga_dac_G(vga_dac_g), + .vga_dac_B(vga_dac_b), + .dram_axi_bridge_s0_araddr(dram_araddr), + .dram_axi_bridge_s0_arlen(dram_arlen), + .dram_axi_bridge_s0_arid(dram_arid), + .dram_axi_bridge_s0_arsize(dram_arsize), + .dram_axi_bridge_s0_arburst(dram_arburst), + .dram_axi_bridge_s0_arvalid(dram_arvalid), + .dram_axi_bridge_s0_awaddr(dram_awaddr), + .dram_axi_bridge_s0_awlen(dram_awlen), + .dram_axi_bridge_s0_awid(dram_awid), + .dram_axi_bridge_s0_awsize(dram_awsize), + .dram_axi_bridge_s0_awburst(dram_awburst), + .dram_axi_bridge_s0_awvalid(dram_awvalid), + .dram_axi_bridge_s0_bresp(dram_bresp), + .dram_axi_bridge_s0_bid(dram_bid), + .dram_axi_bridge_s0_bvalid(dram_bvalid), + .dram_axi_bridge_s0_bready(dram_bready), + .dram_axi_bridge_s0_arready(dram_arready), + .dram_axi_bridge_s0_awready(dram_awready), + .dram_axi_bridge_s0_rready(dram_rready), + .dram_axi_bridge_s0_rdata(dram_rdata), + .dram_axi_bridge_s0_rresp(dram_rresp), + .dram_axi_bridge_s0_rlast(dram_rlast), + .dram_axi_bridge_s0_rid(dram_rid), + .dram_axi_bridge_s0_rvalid(dram_rvalid), + .dram_axi_bridge_s0_wlast(dram_wlast), + .dram_axi_bridge_s0_wvalid(dram_wvalid), + .dram_axi_bridge_s0_wdata(dram_wdata), + .dram_axi_bridge_s0_wstrb(dram_wstrb), + .dram_axi_bridge_s0_wready(dram_wready), + .io_axi_bridge_s0_awid(mmio_full_awid), + .io_axi_bridge_s0_awaddr(mmio_full_awaddr), + .io_axi_bridge_s0_awlen(mmio_full_awlen), + .io_axi_bridge_s0_awsize(mmio_full_awsize), + .io_axi_bridge_s0_awburst(mmio_full_awburst), + .io_axi_bridge_s0_awlock(mmio_full_awlock), + .io_axi_bridge_s0_awcache(mmio_full_awcache), + .io_axi_bridge_s0_awprot(mmio_full_awprot), + .io_axi_bridge_s0_awqos(mmio_full_awqos), + .io_axi_bridge_s0_awregion(4'b0), + .io_axi_bridge_s0_awvalid(mmio_full_awvalid), + .io_axi_bridge_s0_awready(mmio_full_awready), + .io_axi_bridge_s0_wdata(mmio_full_wdata), + .io_axi_bridge_s0_wstrb(mmio_full_wstrb), + .io_axi_bridge_s0_wlast(mmio_full_wlast), + .io_axi_bridge_s0_wvalid(mmio_full_wvalid), + .io_axi_bridge_s0_wready(mmio_full_wready), + .io_axi_bridge_s0_bid(mmio_full_bid), + .io_axi_bridge_s0_bresp(mmio_full_bresp), + .io_axi_bridge_s0_bvalid(mmio_full_bvalid), + .io_axi_bridge_s0_bready(mmio_full_bready), + .io_axi_bridge_s0_arid(mmio_full_arid), + .io_axi_bridge_s0_araddr(mmio_full_araddr), + .io_axi_bridge_s0_arlen(mmio_full_arlen), + .io_axi_bridge_s0_arsize(mmio_full_arsize), + .io_axi_bridge_s0_arburst(mmio_full_arburst), + .io_axi_bridge_s0_arlock(mmio_full_arlock), + .io_axi_bridge_s0_arcache(mmio_full_arcache), + .io_axi_bridge_s0_arprot(mmio_full_arprot), + .io_axi_bridge_s0_arqos(mmio_full_arqos), + .io_axi_bridge_s0_arregion(4'b0), + .io_axi_bridge_s0_arvalid(mmio_full_arvalid), + .io_axi_bridge_s0_arready(mmio_full_arready), + .io_axi_bridge_s0_rid(mmio_full_rid), + .io_axi_bridge_s0_rdata(mmio_full_rdata), + .io_axi_bridge_s0_rresp(mmio_full_rresp), + .io_axi_bridge_s0_rlast(mmio_full_rlast), + .io_axi_bridge_s0_rvalid(mmio_full_rvalid), + .io_axi_bridge_s0_rready(mmio_full_rready), + .intc_0_interrupt_sender_irq(), //TODO + //TODO TODO TODO + .pixfifo_avalon_dc_buffer_sink_ready(), + .pixfifo_avalon_dc_buffer_sink_startofpacket(1), + .pixfifo_avalon_dc_buffer_sink_endofpacket(0), + .pixfifo_avalon_dc_buffer_sink_valid(1), + .pixfifo_avalon_dc_buffer_sink_data({10'h3ff, 10'h000, 10'h000}), + .sys_clock_out_clk_1_clk(sys_clk), + .sys_rst_out_reset_1_reset_n(sys_rst_n) + ); + + w3d_top w3d + ( + .clk(sys_clk), + .rst_n(sys_rst_n), + .srst_n(sys_srst_n), // output + + .dram_awvalid, + .dram_awready, + .dram_awid, + .dram_awlen, + .dram_awsize, + .dram_awburst, + .dram_awaddr, + .dram_wvalid, + .dram_wready, + .dram_wdata, + .dram_wlast, + .dram_wstrb, + .dram_bvalid, + .dram_bready, + .dram_bid, + .dram_bresp, + .dram_arvalid, + .dram_arready, + .dram_arid, + .dram_arlen, + .dram_arsize, + .dram_arburst, + .dram_araddr, + .dram_rvalid, + .dram_rready, + .dram_rid, + .dram_rdata, + .dram_rresp, + .dram_rlast, + + .mmio_awvalid, + .mmio_awready, + .mmio_awaddr, + .mmio_wvalid, + .mmio_wready, + .mmio_wdata, + .mmio_bvalid, + .mmio_bready, + .mmio_arvalid, + .mmio_arready, + .mmio_araddr, + .mmio_rvalid, + .mmio_rready, + .mmio_rdata, + + //TODO Altera Virtual JTAG + .jtag_tck(0), + .jtag_tms(0), + .jtag_tdi(0), + .jtag_tdo() + ); + + /*defparam + dram_bridge.C_AXI_ID_WIDTH = 8, + dram_bridge.C_AXI_ADDR_WIDTH = 32, + dram_bridge.C_AXI_DATA_WIDTH = 32; + + axi2axi3 dram_bridge + ( + .S_AXI_ACLK(sys_clk), + .S_AXI_ARESETN(sys_srst_n), + + .S_AXI_AWVALID(dram_awvalid), + .S_AXI_AWREADY(dram_awready), + .S_AXI_AWID(dram_awid), + .S_AXI_AWADDR(dram_awaddr), + .S_AXI_AWLEN(dram_awlen), + .S_AXI_AWSIZE(dram_awsize), + .S_AXI_AWBURST(dram_awburst), + .S_AXI_AWLOCK(0), + .S_AXI_AWCACHE(4'b0011), // Normal non-cacheable, non-bufferable + .S_AXI_AWPROT(3'b0), + .S_AXI_AWQOS(4'b0), + + .S_AXI_WVALID(dram_wvalid), + .S_AXI_WREADY(dram_wready), + .S_AXI_WDATA(dram_wdata), + .S_AXI_WSTRB(dram_wstrb), + .S_AXI_WLAST(dram_wlast), + + .S_AXI_BVALID(dram_bvalid), + .S_AXI_BREADY(dram_bready), + .S_AXI_BID(dram_bid), + .S_AXI_BRESP(dram_bresp), + + .S_AXI_ARVALID(dram_arvalid), + .S_AXI_ARREADY(dram_arready), + .S_AXI_ARID(dram_arid), + .S_AXI_ARADDR(dram_araddr), + .S_AXI_ARLEN(dram_arlen), + .S_AXI_ARSIZE(dram_arsize), + .S_AXI_ARBURST(dram_arburst), + .S_AXI_ARLOCK(0), + .S_AXI_ARCACHE(4'b0011), // Normal non-cacheable, non-bufferable + .S_AXI_ARPROT(3'b0), + .S_AXI_ARQOS(4'b0), + + .S_AXI_RVALID(dram_rvalid), + .S_AXI_RREADY(dram_rready), + .S_AXI_RID(dram_rid), + .S_AXI_RDATA(dram_rdata), + .S_AXI_RLAST(dram_rlast), + .S_AXI_RRESP(dram_rresp), + + .M_AXI_AWVALID(dram_axi3_awvalid), + .M_AXI_AWREADY(dram_axi3_awready), + .M_AXI_AWID(dram_axi3_awid), + .M_AXI_AWADDR(dram_axi3_awaddr), + .M_AXI_AWLEN(dram_axi3_awlen), + .M_AXI_AWSIZE(dram_axi3_awsize), + .M_AXI_AWBURST(dram_axi3_awburst), + .M_AXI_AWLOCK(dram_axi3_awlock), + .M_AXI_AWCACHE(dram_axi3_awcache), + .M_AXI_AWPROT(dram_axi3_awprot), + .M_AXI_AWQOS(), + + .M_AXI_WVALID(dram_axi3_wvalid), + .M_AXI_WREADY(dram_axi3_wready), + .M_AXI_WID(dram_axi3_wid), + .M_AXI_WDATA(dram_axi3_wdata), + .M_AXI_WSTRB(dram_axi3_wstrb), + .M_AXI_WLAST(dram_axi3_wlast), + .M_AXI_BVALID(dram_axi3_bvalid), + .M_AXI_BREADY(dram_axi3_bready), + .M_AXI_BID(dram_axi3_bid), + .M_AXI_BRESP(dram_axi3_bresp), + .M_AXI_ARVALID(dram_axi3_arvalid), + .M_AXI_ARREADY(dram_axi3_arready), + .M_AXI_ARID(dram_axi3_arid), + .M_AXI_ARADDR(dram_axi3_araddr), + .M_AXI_ARLEN(dram_axi3_arlen), + .M_AXI_ARSIZE(dram_axi3_arsize), + .M_AXI_ARBURST(dram_axi3_arburst), + .M_AXI_ARLOCK(dram_axi3_arlock), + .M_AXI_ARCACHE(dram_axi3_arcache), + .M_AXI_ARPROT(dram_axi3_arprot), + .M_AXI_ARQOS(), + .M_AXI_RVALID(dram_axi3_rvalid), + .M_AXI_RREADY(dram_axi3_rready), + .M_AXI_RID(dram_axi3_rid), + .M_AXI_RDATA(dram_axi3_rdata), + .M_AXI_RLAST(dram_axi3_rlast), + .M_AXI_RRESP(dram_axi3_rresp) + );*/ + + defparam + mmio_bridge.C_AXI_ID_WIDTH = 8, + mmio_bridge.C_AXI_ADDR_WIDTH = 32, + mmio_bridge.C_AXI_DATA_WIDTH = 32; + + axilite2axi mmio_bridge + ( + .ACLK(sys_clk), + .ARESETN(sys_srst_n), + + .S_AXI_AWVALID(mmio_awvalid), + .S_AXI_AWREADY(mmio_awready), + .S_AXI_AWADDR(mmio_awaddr), + .S_AXI_AWPROT(3'b0), + .S_AXI_WVALID(mmio_wvalid), + .S_AXI_WREADY(mmio_wready), + .S_AXI_WDATA(mmio_wdata), + .S_AXI_WSTRB(4'b1111), + .S_AXI_BVALID(mmio_bvalid), + .S_AXI_BREADY(mmio_bready), + .S_AXI_BRESP(), + .S_AXI_ARVALID(mmio_arvalid), + .S_AXI_ARREADY(mmio_arready), + .S_AXI_ARADDR(mmio_araddr), + .S_AXI_ARPROT(3'b0), + .S_AXI_RVALID(mmio_rvalid), + .S_AXI_RREADY(mmio_rready), + .S_AXI_RDATA(mmio_rdata), + .S_AXI_RRESP(), + + .M_AXI_AWVALID(mmio_full_awvalid), + .M_AXI_AWREADY(mmio_full_awready), + .M_AXI_AWID(mmio_full_awid), + .M_AXI_AWADDR(mmio_full_awaddr), + .M_AXI_AWLEN(mmio_full_awlen), + .M_AXI_AWSIZE(mmio_full_awsize), + .M_AXI_AWBURST(mmio_full_awburst), + .M_AXI_AWLOCK(mmio_full_awlock), + .M_AXI_AWCACHE(mmio_full_awcache), + .M_AXI_AWPROT(mmio_full_awprot), + .M_AXI_AWQOS(mmio_full_awqos), + .M_AXI_WVALID(mmio_full_wvalid), + .M_AXI_WREADY(mmio_full_wready), + .M_AXI_WDATA(mmio_full_wdata), + .M_AXI_WSTRB(mmio_full_wstrb), + .M_AXI_WLAST(mmio_full_wlast), + .M_AXI_BVALID(mmio_full_bvalid), + .M_AXI_BREADY(mmio_full_bready), + .M_AXI_BID(mmio_full_bid), + .M_AXI_BRESP(mmio_full_bresp), + .M_AXI_ARVALID(mmio_full_arvalid), + .M_AXI_ARREADY(mmio_full_arready), + .M_AXI_ARID(mmio_full_arid), + .M_AXI_ARADDR(mmio_full_araddr), + .M_AXI_ARLEN(mmio_full_arlen), + .M_AXI_ARSIZE(mmio_full_arsize), + .M_AXI_ARBURST(mmio_full_arburst), + .M_AXI_ARLOCK(mmio_full_arlock), + .M_AXI_ARCACHE(mmio_full_arcache), + .M_AXI_ARPROT(mmio_full_arprot), + .M_AXI_ARQOS(mmio_full_arqos), + .M_AXI_RVALID(mmio_full_rvalid), + .M_AXI_RREADY(mmio_full_rready), + .M_AXI_RID(mmio_full_rid), + .M_AXI_RDATA(mmio_full_rdata), + .M_AXI_RLAST(mmio_full_rlast), + .M_AXI_RRESP(mmio_full_rresp) + ); + +endmodule |