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-rw-r--r--rtl/gfx/gfx_top.sv4
-rw-r--r--rtl/gfx/gfx_xbar_sched.sv95
-rw-r--r--rtl/gfx/gfx_xbar_vram.sv39
3 files changed, 130 insertions, 8 deletions
diff --git a/rtl/gfx/gfx_top.sv b/rtl/gfx/gfx_top.sv
index 99f2133..93d5585 100644
--- a/rtl/gfx/gfx_top.sv
+++ b/rtl/gfx/gfx_top.sv
@@ -10,7 +10,7 @@ import gfx::*;
if_axil.s host_ctrl
);
- if_axib data_mem(), insn_mem();
+ if_axib data_mem(), insn_mem(), sched_vram();
if_axil bootrom_axi(), debug_axi(), host_ctrl_axi(), sched_axi(), shader_0_axi();
logic irq_host_ctrl;
@@ -64,6 +64,7 @@ import gfx::*;
.sched(sched_axi.s),
+ .vram(sched_vram.m),
.debug(debug_axi.m),
.bootrom(bootrom_axi.m),
.shader_0(shader_0_axi.m),
@@ -75,6 +76,7 @@ import gfx::*;
.clk,
.srst_n,
.vram,
+ .sched(sched_vram.s),
.shader_0_data(data_mem.s),
.shader_0_insn(insn_mem.s)
);
diff --git a/rtl/gfx/gfx_xbar_sched.sv b/rtl/gfx/gfx_xbar_sched.sv
index 32305cd..f0aef84 100644
--- a/rtl/gfx/gfx_xbar_sched.sv
+++ b/rtl/gfx/gfx_xbar_sched.sv
@@ -6,12 +6,16 @@ import gfx::*;
if_axil.s sched,
+ if_axib.m vram,
+
if_axil.m debug,
bootrom,
shader_0,
host_ctrl
);
+ if_axil vram_lite();
+
localparam word
BOOTROM_MASK = 32'hfff0_0000,
DEBUG_BASE = 32'h0020_0000,
@@ -19,13 +23,16 @@ import gfx::*;
HOST_CTRL_BASE = 32'h0030_0000,
HOST_CTRL_MASK = 32'hfff0_0000,
SHADER_0_BASE = 32'h0100_0000,
- SHADER_0_MASK = 32'hfff0_0000;
+ SHADER_0_MASK = 32'hfff0_0000,
+ VRAM_BASE = 32'h1c00_0000,
+ VRAM_MASK = 32'hfc00_0000;
defparam xbar.NM = 1;
- defparam xbar.NS = 4;
+ defparam xbar.NS = 5;
defparam xbar.OPT_LOWPOWER = 0;
defparam xbar.SLAVE_ADDR = {
+ VRAM_BASE,
SHADER_0_BASE,
HOST_CTRL_BASE,
DEBUG_BASE,
@@ -33,6 +40,7 @@ import gfx::*;
};
defparam xbar.SLAVE_MASK = {
+ VRAM_MASK,
SHADER_0_MASK,
HOST_CTRL_MASK,
DEBUG_MASK,
@@ -69,6 +77,7 @@ import gfx::*;
.S_AXI_RRESP(),
.M_AXI_AWADDR({
+ vram_lite.m.awaddr,
shader_0.awaddr,
host_ctrl.awaddr,
debug.awaddr,
@@ -76,12 +85,14 @@ import gfx::*;
}),
.M_AXI_AWPROT(),
.M_AXI_AWVALID({
+ vram_lite.m.awvalid,
shader_0.awvalid,
host_ctrl.awvalid,
debug.awvalid,
bootrom.awvalid
}),
.M_AXI_AWREADY({
+ vram_lite.m.awready,
shader_0.awready,
host_ctrl.awready,
debug.awready,
@@ -89,6 +100,7 @@ import gfx::*;
}),
.M_AXI_WDATA({
+ vram_lite.m.wdata,
shader_0.wdata,
host_ctrl.wdata,
debug.wdata,
@@ -96,12 +108,14 @@ import gfx::*;
}),
.M_AXI_WSTRB(),
.M_AXI_WVALID({
+ vram_lite.m.wvalid,
shader_0.wvalid,
host_ctrl.wvalid,
debug.wvalid,
bootrom.wvalid
}),
.M_AXI_WREADY({
+ vram_lite.m.wready,
shader_0.wready,
host_ctrl.wready,
debug.wready,
@@ -110,12 +124,14 @@ import gfx::*;
.M_AXI_BRESP('0),
.M_AXI_BVALID({
+ vram_lite.m.bvalid,
shader_0.bvalid,
host_ctrl.bvalid,
debug.bvalid,
bootrom.bvalid
}),
.M_AXI_BREADY({
+ vram_lite.m.bready,
shader_0.bready,
host_ctrl.bready,
debug.bready,
@@ -123,6 +139,7 @@ import gfx::*;
}),
.M_AXI_ARADDR({
+ vram_lite.m.araddr,
shader_0.araddr,
host_ctrl.araddr,
debug.araddr,
@@ -130,12 +147,14 @@ import gfx::*;
}),
.M_AXI_ARPROT(),
.M_AXI_ARVALID({
+ vram_lite.m.arvalid,
shader_0.arvalid,
host_ctrl.arvalid,
debug.arvalid,
bootrom.arvalid
}),
.M_AXI_ARREADY({
+ vram_lite.m.arready,
shader_0.arready,
host_ctrl.arready,
debug.arready,
@@ -143,6 +162,7 @@ import gfx::*;
}),
.M_AXI_RDATA({
+ vram_lite.m.rdata,
shader_0.rdata,
host_ctrl.rdata,
debug.rdata,
@@ -150,12 +170,14 @@ import gfx::*;
}),
.M_AXI_RRESP('0),
.M_AXI_RVALID({
+ vram_lite.m.rvalid,
shader_0.rvalid,
host_ctrl.rvalid,
debug.rvalid,
bootrom.rvalid
}),
.M_AXI_RREADY({
+ vram_lite.m.rready,
shader_0.rready,
host_ctrl.rready,
debug.rready,
@@ -163,4 +185,73 @@ import gfx::*;
})
);
+ defparam
+ vram_bridge.C_AXI_ID_WIDTH = 8,
+ vram_bridge.C_AXI_ADDR_WIDTH = 32,
+ vram_bridge.C_AXI_DATA_WIDTH = 32;
+
+ axilite2axi vram_bridge
+ (
+ .ACLK(clk),
+ .ARESETN(srst_n),
+
+ .S_AXI_AWVALID(vram_lite.s.awvalid),
+ .S_AXI_AWREADY(vram_lite.s.awready),
+ .S_AXI_AWADDR(vram_lite.s.awaddr),
+ .S_AXI_AWPROT(3'b0),
+ .S_AXI_WVALID(vram_lite.s.wvalid),
+ .S_AXI_WREADY(vram_lite.s.wready),
+ .S_AXI_WDATA(vram_lite.s.wdata),
+ .S_AXI_WSTRB(4'b1111),
+ .S_AXI_BVALID(vram_lite.s.bvalid),
+ .S_AXI_BREADY(vram_lite.s.bready),
+ .S_AXI_BRESP(),
+ .S_AXI_ARVALID(vram_lite.s.arvalid),
+ .S_AXI_ARREADY(vram_lite.s.arready),
+ .S_AXI_ARADDR(vram_lite.s.araddr),
+ .S_AXI_ARPROT(3'b0),
+ .S_AXI_RVALID(vram_lite.s.rvalid),
+ .S_AXI_RREADY(vram_lite.s.rready),
+ .S_AXI_RDATA(vram_lite.s.rdata),
+ .S_AXI_RRESP(),
+
+ .M_AXI_AWVALID(vram.awvalid),
+ .M_AXI_AWREADY(vram.awready),
+ .M_AXI_AWID(vram.awid),
+ .M_AXI_AWADDR(vram.awaddr),
+ .M_AXI_AWLEN(vram.awlen),
+ .M_AXI_AWSIZE(vram.awsize),
+ .M_AXI_AWBURST(vram.awburst),
+ .M_AXI_AWLOCK(),
+ .M_AXI_AWCACHE(),
+ .M_AXI_AWPROT(),
+ .M_AXI_AWQOS(),
+ .M_AXI_WVALID(vram.wvalid),
+ .M_AXI_WREADY(vram.wready),
+ .M_AXI_WDATA(vram.wdata),
+ .M_AXI_WSTRB(vram.wstrb),
+ .M_AXI_WLAST(vram.wlast),
+ .M_AXI_BVALID(vram.bvalid),
+ .M_AXI_BREADY(vram.bready),
+ .M_AXI_BID(vram.bid),
+ .M_AXI_BRESP(vram.bresp),
+ .M_AXI_ARVALID(vram.arvalid),
+ .M_AXI_ARREADY(vram.arready),
+ .M_AXI_ARID(vram.arid),
+ .M_AXI_ARADDR(vram.araddr),
+ .M_AXI_ARLEN(vram.arlen),
+ .M_AXI_ARSIZE(vram.arsize),
+ .M_AXI_ARBURST(vram.arburst),
+ .M_AXI_ARLOCK(),
+ .M_AXI_ARCACHE(),
+ .M_AXI_ARPROT(),
+ .M_AXI_ARQOS(),
+ .M_AXI_RVALID(vram.rvalid),
+ .M_AXI_RREADY(vram.rready),
+ .M_AXI_RID(vram.rid),
+ .M_AXI_RDATA(vram.rdata),
+ .M_AXI_RLAST(vram.rlast),
+ .M_AXI_RRESP(vram.rresp)
+ );
+
endmodule
diff --git a/rtl/gfx/gfx_xbar_vram.sv b/rtl/gfx/gfx_xbar_vram.sv
index 3ce8425..c643948 100644
--- a/rtl/gfx/gfx_xbar_vram.sv
+++ b/rtl/gfx/gfx_xbar_vram.sv
@@ -3,17 +3,17 @@ module gfx_xbar_vram
input logic clk,
srst_n,
- if_axib.s shader_0_data,
+ if_axib.s sched,
+ shader_0_data,
shader_0_insn,
if_axib.m vram
);
- defparam xbar.NM = 2;
- defparam xbar.NS = 1;
- defparam xbar.OPT_LOWPOWER = 0;
-
defparam
+ xbar.NM = 3,
+ xbar.NS = 1,
+ xbar.OPT_LOWPOWER = 0,
xbar.SLAVE_ADDR = '0,
xbar.SLAVE_MASK = '0,
xbar.C_AXI_ID_WIDTH = 8;
@@ -24,30 +24,37 @@ module gfx_xbar_vram
.S_AXI_ARESETN(srst_n),
.S_AXI_AWVALID({
+ sched.awvalid,
shader_0_data.awvalid,
shader_0_insn.awvalid
}),
.S_AXI_AWREADY({
+ sched.awready,
shader_0_data.awready,
shader_0_insn.awready
}),
.S_AXI_AWID({
+ sched.awid,
shader_0_data.awid,
shader_0_insn.awid
}),
.S_AXI_AWADDR({
+ sched.awaddr,
shader_0_data.awaddr,
shader_0_insn.awaddr
}),
.S_AXI_AWLEN({
+ sched.awlen,
shader_0_data.awlen,
shader_0_insn.awlen
}),
.S_AXI_AWSIZE({
+ sched.awsize,
shader_0_data.awsize,
shader_0_insn.awsize
}),
.S_AXI_AWBURST({
+ sched.awburst,
shader_0_data.awburst,
shader_0_insn.awburst
}),
@@ -57,68 +64,84 @@ module gfx_xbar_vram
.S_AXI_AWQOS('0),
.S_AXI_WVALID({
+ sched.wvalid,
shader_0_data.wvalid,
shader_0_insn.wvalid
}),
.S_AXI_WREADY({
+ sched.wready,
shader_0_data.wready,
shader_0_insn.wready
}),
.S_AXI_WDATA({
+ sched.wdata,
shader_0_data.wdata,
shader_0_insn.wdata
}),
.S_AXI_WSTRB({
+ sched.wstrb,
shader_0_data.wstrb,
shader_0_insn.wstrb
}),
.S_AXI_WLAST({
+ sched.wlast,
shader_0_data.wlast,
shader_0_insn.wlast
}),
.S_AXI_BVALID({
+ sched.bvalid,
shader_0_data.bvalid,
shader_0_insn.bvalid
}),
.S_AXI_BREADY({
+ sched.bready,
shader_0_data.bready,
shader_0_insn.bready
}),
.S_AXI_BID({
+ sched.bid,
shader_0_data.bid,
shader_0_insn.bid
}),
.S_AXI_BRESP({
+ sched.bresp,
shader_0_data.bresp,
shader_0_insn.bresp
}),
.S_AXI_ARVALID({
+ sched.arvalid,
shader_0_data.arvalid,
shader_0_insn.arvalid
}),
.S_AXI_ARREADY({
+ sched.arready,
shader_0_data.arready,
shader_0_insn.arready
}),
.S_AXI_ARID({
+ sched.arid,
shader_0_data.arid,
shader_0_insn.arid
}),
.S_AXI_ARADDR({
+ sched.araddr,
shader_0_data.araddr,
shader_0_insn.araddr
}),
.S_AXI_ARLEN({
+ sched.arlen,
shader_0_data.arlen,
shader_0_insn.arlen
}),
.S_AXI_ARSIZE({
+ sched.arsize,
shader_0_data.arsize,
shader_0_insn.arsize
}),
.S_AXI_ARBURST({
+ sched.arburst,
shader_0_data.arburst,
shader_0_insn.arburst
}),
@@ -128,26 +151,32 @@ module gfx_xbar_vram
.S_AXI_ARQOS('0),
.S_AXI_RVALID({
+ sched.rvalid,
shader_0_data.rvalid,
shader_0_insn.rvalid
}),
.S_AXI_RREADY({
+ sched.rready,
shader_0_data.rready,
shader_0_insn.rready
}),
.S_AXI_RID({
+ sched.rid,
shader_0_data.rid,
shader_0_insn.rid
}),
.S_AXI_RDATA({
+ sched.rdata,
shader_0_data.rdata,
shader_0_insn.rdata
}),
.S_AXI_RRESP({
+ sched.rresp,
shader_0_data.rresp,
shader_0_insn.rresp
}),
.S_AXI_RLAST({
+ sched.rlast,
shader_0_data.rlast,
shader_0_insn.rlast
}),
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 08:36:35 +0000